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| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2022-07-05 09:20:22 +0200 |
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| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2022-07-05 09:20:22 +0200 |
| commit | ce05f30dc3a04ca32f91f9fd2a3de7e0b52b0417 (patch) | |
| tree | 4917d1d2482e30985f9ca0ccf51a52ea8320db6c /tools/perf/scripts/python | |
| parent | clk: renesas: r8a779f0: Add HSCIF clocks (diff) | |
| parent | dt-bindings: clock: r9a07g043-cpg: Add Renesas RZ/Five CPG Clock and Reset De... (diff) | |
| download | linux-ce05f30dc3a04ca32f91f9fd2a3de7e0b52b0417.tar.gz linux-ce05f30dc3a04ca32f91f9fd2a3de7e0b52b0417.zip | |
Merge tag 'renesas-r9a07g043-dt-binding-defs-tag2' into HEAD
Renesas RZ/Five DT Binding Definitions
Clock and reset definitions for the Renesas RZ/Five (R9A07G043) SoC,
shared by driver and DT source files.
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions