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| author | Eric Lin <eric.lin@sifive.com> | 2025-02-12 17:21:39 -0800 |
|---|---|---|
| committer | Namhyung Kim <namhyung@kernel.org> | 2025-03-10 14:15:38 -0700 |
| commit | 2e3a13d6b74ee0ca59b2243878b7b6e0dddbcf6b (patch) | |
| tree | 3e5d3e5068a0eee787d63f274a5d9ed4bf875497 /tools/perf/util/python.c | |
| parent | perf vendor events riscv: Add SiFive Bullet version 0x0d events (diff) | |
| download | linux-2e3a13d6b74ee0ca59b2243878b7b6e0dddbcf6b.tar.gz linux-2e3a13d6b74ee0ca59b2243878b7b6e0dddbcf6b.zip | |
perf vendor events riscv: Add SiFive P550 events
The SiFive Performance P550 core features an out-of-order
microarchitecture which exposes the same PMU events as Bullet,
plus events for UTLB hits and PTE cache misses/hits.
Add support for specifying these events using symbolic names.
Signed-off-by: Eric Lin <eric.lin@sifive.com>
Co-developed-by: Samuel Holland <samuel.holland@sifive.com>
Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
Reviewed-by: Ian Rogers <irogers@google.com>
Tested-by: Ian Rogers <irogers@google.com>
Tested-by: Atish Patra <atishp@rivosinc.com>
Link: https://lore.kernel.org/r/20250213220341.3215660-7-samuel.holland@sifive.com
Signed-off-by: Namhyung Kim <namhyung@kernel.org>
Diffstat (limited to 'tools/perf/util/python.c')
0 files changed, 0 insertions, 0 deletions