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| author | Derek Basehore <dbasehore@chromium.org> | 2018-03-13 13:37:19 -0700 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2018-03-14 00:37:22 +0100 |
| commit | 4ee3fd4abeca30d530fe67972f1964f7454259d6 (patch) | |
| tree | 466579a6610cb0f25a0b836c27dad771367c36aa /tools/perf/util/scripting-engines/trace-event-python.c | |
| parent | clk: rockchip: Restore the clock phase after the rate was changed (diff) | |
| download | linux-4ee3fd4abeca30d530fe67972f1964f7454259d6.tar.gz linux-4ee3fd4abeca30d530fe67972f1964f7454259d6.zip | |
clk: rockchip: Add 1.6GHz PLL rate for rk3399
We need this rate to generate 100, 200, and 228.57MHz from the same
PLL. 228.57MHz is useful for a pixel clock when the VPLL is used for
an external display.
Signed-off-by: Derek Basehore <dbasehore@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'tools/perf/util/scripting-engines/trace-event-python.c')
0 files changed, 0 insertions, 0 deletions