diff options
| -rw-r--r-- | arch/arm64/boot/dts/rockchip/Makefile | 1 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/rockchip/rk3566-qnap-ts133.dts | 71 |
2 files changed, 72 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index a02510bb9c48..1bb97cd6e4b0 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -114,6 +114,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-powkiddy-rgb20sx.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-powkiddy-rgb30.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-powkiddy-rk2023.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-powkiddy-x55.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-qnap-ts133.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-a.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-b.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-radxa-cm3-io.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3566-qnap-ts133.dts b/arch/arm64/boot/dts/rockchip/rk3566-qnap-ts133.dts new file mode 100644 index 000000000000..d605a712de5b --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3566-qnap-ts133.dts @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * Copyright (c) 2024 Heiko Stuebner <heiko@sntech.de> + */ + +/dts-v1/; + +#include "rk3566.dtsi" +#include "rk3568-qnap-tsx33.dtsi" + +/ { + model = "Qnap TS-133-2G NAS System 1-Bay"; + compatible = "qnap,ts133", "rockchip,rk3566"; + + aliases { + ethernet0 = &gmac1; + }; +}; + +&gmac1 { + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>; + assigned-clock-rates = <0>, <125000000>; + clock_in_out = "output"; + phy-handle = <&rgmii_phy0>; + phy-mode = "rgmii-id"; + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m1_miim + &gmac1m1_tx_bus2 + &gmac1m1_rx_bus2 + &gmac1m1_rgmii_clk + &gmac1m1_rgmii_bus>; + status = "okay"; +}; + +&mcu { + compatible = "qnap,ts133-mcu"; +}; + +&mdio1 { + rgmii_phy0: ethernet-phy@3 { + /* Motorcomm YT8521 phy */ + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x3>; + pinctrl-0 = <ð_phy0_reset_pin>; + pinctrl-names = "default"; + reset-assert-us = <10000>; + reset-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_LOW>; + }; +}; + +&pinctrl { + gmac1 { + eth_phy0_reset_pin: eth-phy0-reset-pin { + rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +/* connected to usb_host1_xhci */ +&usb2phy0_host { + phy-supply = <&vcc5v0_otg>; + status = "okay"; +}; + +/* USB3 port on backside */ +&usb_host1_xhci { + dr_mode = "host"; + status = "okay"; +}; |