diff options
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 1673d3596305..dfa235aeed89 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -49,6 +49,7 @@ #include "clk_mgr.h" + #define DC_LOGGER_INIT(logger) #define CTX \ @@ -346,6 +347,7 @@ void dcn10_log_hw_state(struct dc *dc, } DTN_INFO("\n"); + DTN_INFO("\nCALCULATED Clocks: dcfclk_khz:%d dcfclk_deep_sleep_khz:%d dispclk_khz:%d\n" "dppclk_khz:%d max_supported_dppclk_khz:%d fclk_khz:%d socclk_khz:%d\n\n", dc->current_state->bw_ctx.bw.dcn.clk.dcfclk_khz, @@ -1952,7 +1954,12 @@ static void update_dpp(struct dpp *dpp, struct dc_plane_state *plane_state) plane_state->format, EXPANSION_MODE_ZERO, plane_state->input_csc_color_matrix, +#ifdef CONFIG_DRM_AMD_DC_DCN2_0 + plane_state->color_space, + NULL); +#else plane_state->color_space); +#endif //set scale and bias registers dcn10_build_prescale_params(&bns_params, plane_state); @@ -2406,6 +2413,12 @@ static void dcn10_apply_ctx_for_surface( &pipe_ctx->ttu_regs); } +#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + /* Program secondary blending tree and writeback pipes */ + if ((stream->num_wb_info > 0) && (dc->hwss.program_all_writeback_pipes_in_tree)) + dc->hwss.program_all_writeback_pipes_in_tree(dc, stream, context); +#endif + if (interdependent_update) lock_all_pipes(dc, context, false); else |