diff options
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c | 32 |
1 files changed, 19 insertions, 13 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c index 0d8a05cf8b1a..8e68e05e3b72 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c @@ -160,6 +160,8 @@ void dcn314_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx struct pipe_ctx *odm_pipe; int opp_cnt = 0; int opp_inst[MAX_PIPES] = {0}; + int odm_slice_width = resource_get_odm_slice_dst_width(pipe_ctx, false); + int last_odm_slice_width = resource_get_odm_slice_dst_width(pipe_ctx, true); opp_cnt = get_odm_config(pipe_ctx, opp_inst); @@ -167,7 +169,7 @@ void dcn314_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx pipe_ctx->stream_res.tg->funcs->set_odm_combine( pipe_ctx->stream_res.tg, opp_inst, opp_cnt, - &pipe_ctx->stream->timing); + odm_slice_width, last_odm_slice_width); else pipe_ctx->stream_res.tg->funcs->set_odm_bypass( pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); @@ -302,7 +304,7 @@ unsigned int dcn314_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsig unsigned int odm_combine_factor = 0; bool two_pix_per_container = false; - two_pix_per_container = optc2_is_two_pixels_per_containter(&stream->timing); + two_pix_per_container = pipe_ctx->stream_res.tg->funcs->is_two_pixels_per_container(&stream->timing); odm_combine_factor = get_odm_config(pipe_ctx, NULL); if (stream->ctx->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) { @@ -332,21 +334,25 @@ unsigned int dcn314_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsig return odm_combine_factor; } -void dcn314_set_pixels_per_cycle(struct pipe_ctx *pipe_ctx) +void dcn314_calculate_pix_rate_divider( + struct dc *dc, + struct dc_state *context, + const struct dc_stream_state *stream) { - uint32_t pix_per_cycle = 1; - uint32_t odm_combine_factor = 1; + struct dce_hwseq *hws = dc->hwseq; + struct pipe_ctx *pipe_ctx = NULL; + unsigned int k1_div = PIXEL_RATE_DIV_NA; + unsigned int k2_div = PIXEL_RATE_DIV_NA; - if (!pipe_ctx || !pipe_ctx->stream || !pipe_ctx->stream_res.stream_enc) - return; + pipe_ctx = resource_get_otg_master_for_stream(&context->res_ctx, stream); - odm_combine_factor = get_odm_config(pipe_ctx, NULL); - if (optc2_is_two_pixels_per_containter(&pipe_ctx->stream->timing) || odm_combine_factor > 1) - pix_per_cycle = 2; + if (pipe_ctx) { + if (hws->funcs.calculate_dccg_k1_k2_values) + hws->funcs.calculate_dccg_k1_k2_values(pipe_ctx, &k1_div, &k2_div); - if (pipe_ctx->stream_res.stream_enc->funcs->set_input_mode) - pipe_ctx->stream_res.stream_enc->funcs->set_input_mode(pipe_ctx->stream_res.stream_enc, - pix_per_cycle); + pipe_ctx->pixel_rate_divider.div_factor1 = k1_div; + pipe_ctx->pixel_rate_divider.div_factor2 = k2_div; + } } void dcn314_resync_fifo_dccg_dio(struct dce_hwseq *hws, struct dc *dc, struct dc_state *context) |