diff options
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h | 10 |
1 files changed, 7 insertions, 3 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h index 2f3bd7648ba7..e3e70c1db040 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h @@ -200,6 +200,7 @@ struct dcn_optc_registers { uint32_t OTG_CRC1_WINDOWB_X_CONTROL_READBACK; uint32_t OTG_CRC1_WINDOWB_Y_CONTROL_READBACK; uint32_t OPTC_CLOCK_CONTROL; + uint32_t OPTC_WIDTH_CONTROL2; }; #define TG_COMMON_MASK_SH_LIST_DCN(mask_sh)\ @@ -329,8 +330,6 @@ struct dcn_optc_registers { SF(GSL_SOURCE_SELECT, GSL2_READY_SOURCE_SEL, mask_sh),\ SF(OTG0_OTG_GLOBAL_CONTROL2, MANUAL_FLOW_CONTROL_SEL, mask_sh) - - #define TG_COMMON_MASK_SH_LIST_DCN1_0(mask_sh)\ TG_COMMON_MASK_SH_LIST_DCN(mask_sh),\ SF(OTG0_OTG_TEST_PATTERN_PARAMETERS, OTG_TEST_PATTERN_INC0, mask_sh),\ @@ -568,7 +567,6 @@ struct dcn_optc_registers { #define TG_REG_FIELD_LIST_DCN3_2(type) \ type OTG_H_TIMING_DIV_MODE_MANUAL; - #define TG_REG_FIELD_LIST_DCN3_5(type) \ type OTG_CRC0_WINDOWA_X_START_READBACK;\ type OTG_CRC0_WINDOWA_X_END_READBACK;\ @@ -590,16 +588,22 @@ struct dcn_optc_registers { type OTG_V_COUNT_STOP;\ type OTG_V_COUNT_STOP_TIMER; +#define TG_REG_FIELD_LIST_DCN401(type) \ + type OPTC_SEGMENT_WIDTH_LAST; + + struct dcn_optc_shift { TG_REG_FIELD_LIST(uint8_t) TG_REG_FIELD_LIST_DCN3_2(uint8_t) TG_REG_FIELD_LIST_DCN3_5(uint8_t) + TG_REG_FIELD_LIST_DCN401(uint8_t) }; struct dcn_optc_mask { TG_REG_FIELD_LIST(uint32_t) TG_REG_FIELD_LIST_DCN3_2(uint32_t) TG_REG_FIELD_LIST_DCN3_5(uint32_t) + TG_REG_FIELD_LIST_DCN401(uint32_t) }; void dcn10_timing_generator_init(struct optc *optc); |