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path: root/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0.h
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Diffstat (limited to 'drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0.h')
-rw-r--r--drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0.h18
1 files changed, 17 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0.h b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0.h
index 1fc4557e6fb4..46b456590a08 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0.h
@@ -28,7 +28,7 @@
#define SMU14_DRIVER_IF_VERSION_INV 0xFFFFFFFF
#define SMU14_DRIVER_IF_VERSION_SMU_V14_0_0 0x7
#define SMU14_DRIVER_IF_VERSION_SMU_V14_0_1 0x6
-#define SMU14_DRIVER_IF_VERSION_SMU_V14_0_2 0x25
+#define SMU14_DRIVER_IF_VERSION_SMU_V14_0_2 0x26
#define FEATURE_MASK(feature) (1ULL << feature)
@@ -46,6 +46,18 @@
#define MAX_DPM_LEVELS 16
#define MAX_PCIE_CONF 3
+#define SMU14_TOOL_SIZE 0x19000
+
+#define CTF_OFFSET_EDGE 5
+#define CTF_OFFSET_HOTSPOT 5
+#define CTF_OFFSET_MEM 5
+
+extern const int decoded_link_speed[5];
+extern const int decoded_link_width[7];
+
+#define DECODE_GEN_SPEED(gen_speed_idx) (decoded_link_speed[gen_speed_idx])
+#define DECODE_LANE_WIDTH(lane_width_idx) (decoded_link_width[lane_width_idx])
+
struct smu_14_0_max_sustainable_clocks {
uint32_t display_clock;
uint32_t phy_clock;
@@ -228,5 +240,9 @@ int smu_v14_0_od_edit_dpm_table(struct smu_context *smu,
void smu_v14_0_set_smu_mailbox_registers(struct smu_context *smu);
+int smu_v14_0_enable_thermal_alert(struct smu_context *smu);
+
+int smu_v14_0_disable_thermal_alert(struct smu_context *smu);
+
#endif
#endif