| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2019-05-16 | riscv: Add the support for c.ebreak check in is_valid_bugaddr() | Vincent Chen | 1 | -1/+6 |
| 2019-05-16 | riscv: support trap-based WARN() | Vincent Chen | 1 | -10/+18 |
| 2017-11-30 | RISC-V: use RISCV_{INT,SHORT} instead of {INT,SHORT} for asm macros | Olof Johansson | 1 | -3/+3 |
| 2017-09-26 | RISC-V: Init and Halt Code | Palmer Dabbelt | 1 | -0/+88 |
