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2020-07-30riscv: Cleanup unnecessary define in asm-offset.cGuo Ren-5/+1
2020-07-30riscv: Enable context trackingGreentime Hu-1/+15
2020-07-30riscv: Enable LOCKDEP_SUPPORT & fixup TRACE_IRQFLAGS_SUPPORTGuo Ren-1/+33
2020-06-09RISC-V: Remove do_IRQ() functionAnup Patel-1/+3
2020-04-09Merge tag 'riscv-for-linus-5.7' of git://git.kernel.org/pub/scm/linux/kernel/...Linus Torvalds-82/+61
2020-03-05riscv: fix seccomp reject syscall code pathTycho Andersen-8/+3
2020-03-03RISC-V: Inline the assembly register save/restore macrosPalmer Dabbelt-82/+61
2020-01-28Merge branch 'sched-core-for-linus' of git://git.kernel.org/pub/scm/linux/ker...Linus Torvalds-2/+2
2019-12-27riscv: reject invalid syscalls below -1David Abdurachmanov-0/+1
2019-12-08sched/rt, riscv: Use CONFIG_PREEMPTIONThomas Gleixner-2/+2
2019-11-22Merge branch 'next/nommu' into for-nextPaul Walmsley-31/+54
2019-11-17riscv: add nommu supportChristoph Hellwig-0/+11
2019-11-05riscv: abstract out CSR names for supervisor vs machine modeChristoph Hellwig-31/+43
2019-10-29riscv: add support for SECCOMP and SECCOMP_FILTERDavid Abdurachmanov-2/+25
2019-10-09RISC-V: entry: Remove unneeded need_resched() loopValentin Schneider-2/+1
2019-10-01RISC-V: Clear load reservations while restoring hart contextsPalmer Dabbelt-1/+20
2019-09-20riscv: Avoid interrupts being erroneously enabled in handle_exception()Vincent Chen-1/+5
2019-08-30riscv: Using CSR numbers to access CSRsBin Meng-3/+3
2019-06-05treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286Thomas Gleixner-9/+1
2019-05-16RISC-V: Access CSRs using CSR numbersAnup Patel-11/+11
2019-01-23RISC-V: Add _TIF_NEED_RESCHED check for kernel thread when CONFIG_PREEMPT=yVincent Chen-1/+17
2019-01-07riscv: add audit supportDavid Abdurachmanov-2/+2
2018-10-22RISC-V: SMP cleanup and new featuresPalmer Dabbelt-1/+0
2018-10-22RISC-V: No need to pass scause as arg to do_IRQ()Anup Patel-1/+0
2018-10-22Extract FPU context operations from entry.SAlan Kao-87/+0
2018-08-13RISC-V: implement low-level interrupt handlingChristoph Hellwig-2/+2
2018-03-14RISC-V: Move to the new GENERIC_IRQ_MULTI_HANDLER handlerPalmer Dabbelt-4/+3
2018-02-20RISC-V: Enable IRQ during exception handlingzongbox@gmail.com-2/+3
2018-01-30riscv: disable SUM in the exception handlerChristoph Hellwig-3/+6
2018-01-07riscv: rename SR_* constants to match the specChristoph Hellwig-4/+4
2017-09-26RISC-V: Task implementationPalmer Dabbelt-0/+464