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path: root/drivers/clk/actions
AgeCommit message (Expand)AuthorLines
2026-01-22clk: actions: owl-divider: convert from divider_round_rate() to divider_deter...Brian Masney-20/+2
2026-01-22clk: actions: owl-composite: convert from owl_divider_helper_round_rate() to ...Brian Masney-8/+3
2025-11-20clk: actions: Fix discarding const qualifier by 'container_of' macroAdrian Barnaś-7/+7
2025-10-06Merge branch 'clk-determine-rate' into clk-nextStephen Boyd-23/+35
2025-09-08clk: actions: owl-pll: convert from round_rate() to determine_rate()Brian Masney-9/+16
2025-09-08clk: actions: owl-factor: convert from round_rate() to determine_rate()Brian Masney-5/+7
2025-09-08clk: actions: owl-divider: convert from round_rate() to determine_rate()Brian Masney-5/+8
2025-09-08clk: actions: owl-composite: convert from round_rate() to determine_rate()Brian Masney-4/+4
2025-08-14clk: remove unneeded 'fast_io' parameter in regmap_configWolfram Sang-1/+0
2023-08-22clk: actions: Convert to devm_platform_ioremap_resource()Yangtao Li-3/+1
2023-07-19clk: Explicitly include correct DT includesRob Herring-3/+1
2023-06-08clk: actions: composite: fact: Switch to determine_rateMaxime Ripard-6/+12
2023-06-08clk: actions: composite: div: Switch to determine_rateMaxime Ripard-5/+11
2023-06-08clk: actions: composite: Add a determine_rate hook for pass clkMaxime Ripard-0/+1
2022-04-22clk: actions: remove redundant assignment after a mask operationColin Ian King-1/+1
2022-03-11clk: actions: Make sentinel elements more obviousJonathan Neuschäfer-29/+31
2022-03-11clk: actions: Terminate clk_div_table with sentinel elementJonathan Neuschäfer-1/+2
2021-11-02clk/actions/owl-factor.c: remove superfluous headersMianhan Liu-1/+0
2021-06-27clk: actions: Add NIC and ETHERNET clock support for Actions S500 SoCCristian Ciocaltea-1/+16
2021-06-27clk: actions: Fix AHPPREDIV-H-AHB clock chain on Owl S500 SoCCristian Ciocaltea-8/+11
2021-06-27clk: actions: Fix bisp_factor_table based clocks on Owl S500 SoCCristian Ciocaltea-15/+29
2021-06-27clk: actions: Fix SD clocks factor table on Owl S500 SoCCristian Ciocaltea-4/+2
2021-06-27clk: actions: Fix UART clock dividers on Owl S500 SoCCristian Ciocaltea-6/+6
2020-07-21clk: actions: Add Actions S500 SoC Reset Management Unit supportCristian Ciocaltea-0/+78
2020-07-21clk: actions: Add APB, DMAC, GPIO clock support for Actions S500 SoCCristian Ciocaltea-0/+9
2020-07-21clk: actions: Fix h_clk for Actions S500 SoCCristian Ciocaltea-1/+1
2019-09-19Merge branches 'clk-cdce-regulator', 'clk-bcm', 'clk-evict-parent-cache' and ...Stephen Boyd-4/+3
2019-09-17clk: actions: Fix factor clk struct member accessManivannan Sadhasivam-4/+3
2019-08-16clk: actions: Don't reference clk_init_data after registrationStephen Boyd-2/+3
2019-05-21treewide: Add SPDX license identifier - Makefile/KconfigThomas Gleixner-0/+2
2019-05-01clk: actions: Use the correct style for SPDX License IdentifierNishad Kamdar-9/+9
2019-02-22clk: actions: Add clock driver for S500 SoCManivannan Sadhasivam-0/+531
2019-02-21clk: actions: Add configurable PLL delayManivannan Sadhasivam-7/+25
2018-10-16clk: actions: Add Actions Semi S900 SoC Reset Management Unit supportManivannan Sadhasivam-0/+82
2018-10-16clk: actions: Add Actions Semi S700 SoC Reset Management Unit supportManivannan Sadhasivam-0/+51
2018-10-16clk: actions: Add Actions Semi Owl SoCs Reset Management Unit supportManivannan Sadhasivam-0/+101
2018-10-16clk: actions: Cache regmap info in private clock descriptorManivannan Sadhasivam-6/+8
2018-07-25clk: actions: Add S700 SoC clock supportSaravanan Sekar-0/+613
2018-07-25clk: actions: Add missing REGMAP_MMIO dependencySaravanan Sekar-0/+1
2018-04-06clk: actions: Add S900 SoC clock supportManivannan Sadhasivam-0/+734
2018-04-06clk: actions: Add pll clock supportManivannan Sadhasivam-0/+287
2018-04-06clk: actions: Add composite clock supportManivannan Sadhasivam-0/+324
2018-04-06clk: actions: Add fixed factor clock supportManivannan Sadhasivam-0/+28
2018-04-06clk: actions: Add factor clock supportManivannan Sadhasivam-0/+306
2018-04-06clk: actions: Add divider clock supportManivannan Sadhasivam-0/+170
2018-04-06clk: actions: Add mux clock supportManivannan Sadhasivam-0/+122
2018-04-06clk: actions: Add gate clock supportManivannan Sadhasivam-0/+151
2018-04-06clk: actions: Add common clock driver supportManivannan Sadhasivam-0/+137