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path: root/drivers/clk/ingenic
AgeCommit message (Expand)AuthorLines
2026-02-21Convert more 'alloc_obj' cases to default GFP_KERNEL argumentsLinus Torvalds-2/+1
2026-02-21Convert 'alloc_flex' family to use the new default GFP_KERNEL argumentLinus Torvalds-1/+1
2026-02-21Convert 'alloc_obj' family to use the new default GFP_KERNEL argumentLinus Torvalds-4/+4
2026-02-21treewide: Replace kmalloc with kmalloc_obj for non-scalar typesKees Cook-8/+7
2025-11-14syscore: Pass context data to callbacksThierry Reding-18/+26
2025-09-08clk: ingenic: x1000-cgu: convert from round_rate() to determine_rate()Brian Masney-9/+10
2025-09-08clk: ingenic: jz4780-cgu: convert from round_rate() to determine_rate()Brian Masney-12/+12
2025-09-08clk: ingenic: cgu: convert from round_rate() to determine_rate()Brian Masney-5/+7
2025-07-26clk: Fix typosBjorn Helgaas-1/+1
2023-06-08clk: ingenic: tcu: Switch to determine_rateMaxime Ripard-8/+11
2023-06-08clk: ingenic: cgu: Switch to determine_rateMaxime Ripard-7/+8
2023-01-25clk: ingenic: jz4760: Update M/N/OD calculation algorithmPaul Cercueil-10/+8
2022-11-01clk: Add Ingenic JZ4755 CGU driverSiarhei Volkau-0/+357
2022-10-27clk: ingenic: Minor cosmetic fixups for X1000Aidan MacDonald-25/+24
2022-10-27clk: ingenic: Add X1000 audio clocksAidan MacDonald-0/+70
2022-10-27clk: ingenic: Add .set_rate_hook() for PLL clocksAidan MacDonald-0/+7
2022-10-27clk: ingenic: Make PLL clock enable_bit and stable_bit optionalAidan MacDonald-5/+19
2022-10-27clk: ingenic: Make PLL clock "od" field optionalAidan MacDonald-9/+19
2022-08-31clk: ingenic-tcu: Properly enable registers before accessing timersAidan MacDonald-10/+5
2022-05-18clk: ingenic-tcu: Fix missing TCU clock for X1000 SoCsAidan MacDonald-10/+25
2022-05-18clk: ingenic: Mark critical clocks in Ingenic SoCsAidan MacDonald-0/+76
2022-05-18clk: ingenic: Allow specifying common clock flagsAidan MacDonald-1/+4
2022-02-17clk: jz4725b: fix mmc0 clock gatingSiarhei Volkau-2/+1
2022-01-06clk: ingenic: Add MDMA and BDMA clocksPaul Cercueil-0/+15
2021-11-14Merge tag 'devicetree-fixes-for-5.16-1' of git://git.kernel.org/pub/scm/linux...Linus Torvalds-7/+7
2021-11-11dt-bindings: Rename Ingenic CGU headers to ingenic,*.hPaul Cercueil-7/+7
2021-11-02clk: ingenic: Fix bugs with divided dividersPaul Cercueil-3/+3
2021-06-27clk: ingenic: Add support for the JZ4760Paul Cercueil-0/+441
2021-06-27clk: ingenic: Support overriding PLLs M/N/OD calc algorithmPaul Cercueil-13/+30
2021-06-27clk: ingenic: Remove pll_info.no_bypass_bitPaul Cercueil-8/+6
2021-06-27clk: ingenic: Read bypass register only when there is onePaul Cercueil-8/+11
2021-06-27clk: Support bypassing dividersPaul Cercueil-29/+42
2020-12-19clk: ingenic: Fix divider calculation with div tablesPaul Cercueil-4/+10
2020-10-13clk: ingenic: Respect CLK_SET_RATE_PARENT in .round_ratePaul Cercueil-0/+2
2020-10-13clk: ingenic: Don't tag custom clocks with CLK_SET_RATE_PARENTPaul Cercueil-7/+7
2020-10-13clk: ingenic: Don't use CLK_SET_RATE_GATE for PLLPaul Cercueil-2/+7
2020-10-13clk: ingenic: Use readl_poll_timeout instead of custom loopPaul Cercueil-26/+29
2020-10-13clk: ingenic: Use to_clk_info() macro for all clocksPaul Cercueil-39/+15
2020-07-27clk: X1000: Add support for calculat REFCLK of USB PHY.周琰杰 (Zhou Yanjie)-1/+83
2020-07-27clk: JZ4780: Reformat the code to align it.周琰杰 (Zhou Yanjie)-45/+45
2020-07-27clk: JZ4780: Add functions for enable and disable USB PHY.周琰杰 (Zhou Yanjie)-30/+35
2020-07-27clk: Ingenic: Add RTC related clocks for Ingenic SoCs.周琰杰 (Zhou Yanjie)-0/+38
2020-05-28clk: ingenic: Mark ingenic_tcu_of_match as __maybe_unusedStephen Boyd-1/+1
2020-05-28clk: X1000: Add FIXDIV for SSI clock of X1000.周琰杰 (Zhou Yanjie)-6/+111
2020-05-28clk: Ingenic: Add CGU driver for X1830.周琰杰 (Zhou Yanjie)-0/+459
2020-05-28clk: Ingenic: Adjust cgu code to make it compatible with X1830.周琰杰 (Zhou Yanjie)-4/+41
2020-05-28clk: Ingenic: Remove unnecessary spinlock when reading registers.周琰杰 (Zhou Yanjie)-11/+1
2020-03-20clk: ingenic/TCU: Fix round_rate returning errorPaul Cercueil-1/+1
2020-03-20clk: ingenic/jz4770: Exit with error if CGU init failedPaul Cercueil-1/+3
2020-03-20clk: JZ4780: Add function for enable the second core.周琰杰 (Zhou Yanjie)-5/+50