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path: root/drivers/clk/mediatek
AgeCommit message (Expand)AuthorLines
2026-02-21Convert 'alloc_flex' family to use the new default GFP_KERNEL argumentLinus Torvalds-1/+1
2026-02-21Convert 'alloc_obj' family to use the new default GFP_KERNEL argumentLinus Torvalds-9/+9
2026-02-21treewide: Replace kmalloc with kmalloc_obj for non-scalar typesKees Cook-10/+10
2026-01-22clk: mediatek: Fix error handling in runtime PM setupHaotian Zhang-5/+7
2026-01-22clk: mediatek: don't select clk-mt8192 for all ARM64 buildsBartosz Golaszewski-1/+1
2026-01-22clk: mediatek: Add mfg_eb as parent to mt8196 mfgpll clocksNicolas Frattaroli-6/+11
2026-01-22clk: mediatek: Refactor pllfh registration to pass deviceNicolas Frattaroli-17/+20
2026-01-22clk: mediatek: Pass device to clk_hw_register for PLLsNicolas Frattaroli-5/+10
2026-01-22clk: mediatek: Refactor pll registration to pass deviceNicolas Frattaroli-32/+34
2026-01-22clk: mediatek: Drop __initconst from gatesSjoerd Simons-4/+4
2025-10-06Merge branch 'clk-determine-rate' into clk-nextStephen Boyd-9/+11
2025-09-21clk: mediatek: Add MT8196 vencsys clock supportLaura Nao-0/+244
2025-09-21clk: mediatek: Add MT8196 vdecsys clock supportLaura Nao-0/+261
2025-09-21clk: mediatek: Add MT8196 ovl1 clock supportLaura Nao-1/+155
2025-09-21clk: mediatek: Add MT8196 ovl0 clock supportLaura Nao-1/+156
2025-09-21clk: mediatek: Add MT8196 disp-ao clock supportLaura Nao-1/+81
2025-09-21clk: mediatek: Add MT8196 disp1 clock supportLaura Nao-1/+171
2025-09-21clk: mediatek: Add MT8196 disp0 clock supportLaura Nao-0/+178
2025-09-21clk: mediatek: Add MT8196 mfg clock supportLaura Nao-0/+158
2025-09-21clk: mediatek: Add MT8196 mdpsys clock supportLaura Nao-0/+194
2025-09-21clk: mediatek: Add MT8196 mcu clock supportLaura Nao-0/+175
2025-09-21clk: mediatek: Add MT8196 I2C clock supportLaura Nao-0/+126
2025-09-21clk: mediatek: Add MT8196 pextpsys clock supportLaura Nao-0/+139
2025-09-21clk: mediatek: Add MT8196 ufssys clock supportLaura Nao-0/+116
2025-09-21clk: mediatek: Add MT8196 peripheral clock supportLaura Nao-1/+144
2025-09-21clk: mediatek: Add MT8196 vlpckgen clock supportLaura Nao-1/+726
2025-09-21clk: mediatek: Add MT8196 topckgen2 clock supportLaura Nao-1/+570
2025-09-21clk: mediatek: Add MT8196 topckgen clock supportLaura Nao-1/+986
2025-09-21clk: mediatek: Add MT8196 apmixedsys clock supportLaura Nao-0/+213
2025-09-21clk: mediatek: clk-mtk: Add MUX_DIV_GATE macroLaura Nao-0/+19
2025-09-21clk: mediatek: clk-gate: Add ops for gates with HW voterLaura Nao-3/+71
2025-09-21clk: mediatek: clk-gate: Refactor mtk_clk_register_gate to use mtk_gate structLaura Nao-33/+19
2025-09-21clk: mediatek: clk-mux: Add ops for mux gates with HW voter and FENCLaura Nao-1/+114
2025-09-21clk: mediatek: clk-mtk: Introduce mtk_clk_get_hwv_regmap()Laura Nao-0/+17
2025-09-21clk: mediatek: clk-mux: Add ops for mux gates with set/clr/upd and FENCLaura Nao-0/+94
2025-09-21clk: mediatek: clk-pll: Add ops for PLLs using set/clr regs and FENCLaura Nao-1/+44
2025-09-21clk: mediatek: clk-pll: Add set/clr regs for shared PLL enable controlLaura Nao-0/+8
2025-09-21clk: mediatek: clk-mux: Do not pass flags to clk_mux_determine_rate_flags()Chen-Yu Tsai-3/+1
2025-09-21clk: mediatek: mt7622-aud: Add missing AFE_MRGIF clockAngeloGioacchino Del Regno-0/+1
2025-09-21clk: mediatek: mt8195-infra_ao: Fix parent for infra_ao_hdmi_26mAngeloGioacchino Del Regno-1/+1
2025-09-08clk: mediatek: pll: convert from round_rate() to determine_rate()Brian Masney-8/+10
2025-02-27clk: mediatek: Add SMI LARBs reset for MT8188Friday Yang-0/+49
2025-02-26clk: mediatek: mt8188-vdo1: Add VDO1_DPI1_HDMI clock for hdmitxAngeloGioacchino Del Regno-0/+11
2024-12-17clk: mediatek: mt2701-img: add missing dummy clkDaniel Golle-0/+1
2024-12-17clk: mediatek: mt2701-mm: add missing dummy clkDaniel Golle-0/+1
2024-12-17clk: mediatek: mt2701-bdp: add missing dummy clkDaniel Golle-0/+1
2024-12-17clk: mediatek: mt2701-aud: fix conversion to mtk_clk_simple_probeDaniel Golle-0/+10
2024-12-17clk: mediatek: mt2701-vdec: fix conversion to mtk_clk_simple_probeDaniel Golle-0/+1
2024-11-14clk: mediatek: Add drivers for MT6735 syscon clock and reset controllersYassine Oudjana-0/+282
2024-11-14clk: mediatek: mt6735-apmixedsys: Fix an error handling path in clk_mt6735_ap...Christophe JAILLET-2/+1