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2025-09-19clk: amlogic: fix recent code refactoringMarek Szyprowski1-1/+1
Commit 4c4e17f27013 ("clk: amlogic: naming consistency alignment") refactored some internals in the g12a meson clock driver. Unfortunately it introduced a bug in the clock init data, which results in the following kernel panic: Unable to handle kernel NULL pointer dereference at virtual address 0000000000000000 Mem abort info: ... Data abort info: ... [0000000000000000] user address but active_mm is swapper Internal error: Oops: 0000000096000004 [#1] SMP Modules linked in: CPU: 4 UID: 0 PID: 1 Comm: swapper/0 Not tainted 6.17.0-rc1+ #11158 PREEMPT Hardware name: Hardkernel ODROID-N2 (DT) pstate: 60000005 (nZCv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--) pc : __clk_register+0x60/0x92c lr : __clk_register+0x48/0x92c ... Call trace: __clk_register+0x60/0x92c (P) devm_clk_hw_register+0x5c/0xd8 meson_eeclkc_probe+0x74/0x110 g12a_clkc_probe+0x2c/0x58 platform_probe+0x5c/0xac really_probe+0xbc/0x298 __driver_probe_device+0x78/0x12c driver_probe_device+0xdc/0x164 __driver_attach+0x9c/0x1ac bus_for_each_dev+0x74/0xd0 driver_attach+0x24/0x30 bus_add_driver+0xe4/0x208 driver_register+0x60/0x128 __platform_driver_register+0x24/0x30 g12a_clkc_driver_init+0x1c/0x28 do_one_initcall+0x64/0x308 kernel_init_freeable+0x27c/0x4f8 kernel_init+0x20/0x1d8 ret_from_fork+0x10/0x20 Code: 52800038 aa0003fc b9010018 52819801 (f9400260) ---[ end trace 0000000000000000 ]--- Fix this by correcting the clock init data. Fixes: 4c4e17f27013 ("clk: amlogic: naming consistency alignment") Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on BananPi M2S Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2025-09-04clk: amlogic: c3-peripherals: use helper for basic composite clocksJerome Brunet1-966/+63
Use the composite clock helpers to define simple composite clocks of the c3-peripherals clock controller. This reduces the verbosity of the controller code on these very simple parts, making maintenance simpler. Reviewed-by: Chuan Liu <chuan.liu@amlogic.com> Link: https://lore.kernel.org/r/20250825-meson-clk-cleanup-24-v2-12-0f402f01e117@baylibre.com Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2025-09-04clk: amlogic: align s4 and c3 pwm clock descriptionsJerome Brunet2-609/+103
s4 and c3 follow exactly the same structure when it comes to PWM clocks but differ in the way these clocks are described, for no obvious reason. Align the description of the pwm clocks of these SoCs with the composite clock helpers. Reviewed-by: Chuan Liu <chuan.liu@amlogic.com> Link: https://lore.kernel.org/r/20250825-meson-clk-cleanup-24-v2-11-0f402f01e117@baylibre.com Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2025-09-04clk: amlogic: add composite clock helpersJerome Brunet1-0/+57
Device composite clocks tend to reproduce the usual sel/div/gate arrangement. Add macros to help define simple composite clocks in the system. The idea is _not_ to replace all instances of mux, div or gate with those macros. It is rather to use it for recurring and/or simple composite clocks, reducing controller verbosity where it makes sense. This should help reviews focus on the tricky parts. Link: https://lore.kernel.org/r/20250825-meson-clk-cleanup-24-v2-10-0f402f01e117@baylibre.com Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2025-09-04clk: amlogic: use the common pclk definitionJerome Brunet4-101/+51
Replace marcros defining pclks with the common one, reducing code duplication. Link: https://lore.kernel.org/r/20250825-meson-clk-cleanup-24-v2-9-0f402f01e117@baylibre.com Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2025-09-04clk: amlogic: introduce a common pclk definitionJerome Brunet7-33/+54
All Amlogic peripheral clocks are more or less the same. The only thing that differs is the parent data. Adapt the common pclk definition so it takes clk_parent_data and can be used by all controllers. Reviewed-by: Chuan Liu <chuan.liu@amlogic.com> Link: https://lore.kernel.org/r/20250825-meson-clk-cleanup-24-v2-8-0f402f01e117@baylibre.com Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2025-09-04clk: amlogic: pclk explicitly use CLK_IGNORE_UNUSEDJerome Brunet10-468/+528
Every usage of CLK_IGNORE_UNUSED should be explicitly motivated and documented. However, the PCLK macros used by most Amlogic platforms are adding that flag systematically. Because of this, all pclks are marked with CLK_IGNORE_UNUSED, without any form of distinction or motivation. This may have been fine in the early days of CCF but it is not anymore. Just removing the flag is not an option at this stage since it could cause regression on existing platforms. Instead, drop the flag from the macro definition and add it to the each clock definition, for the existing clocks. This makes quite a nasty change but it will make it a lot easier for people to contribute to fixing the problem, clock by clock. It will also prevent new platform from being added with a silent use of the flag. Reviewed-by: Chuan Liu <chuan.liu@amlogic.com> Link: https://lore.kernel.org/r/20250825-meson-clk-cleanup-24-v2-7-0f402f01e117@baylibre.com Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2025-09-04clk: amlogic: drop CLK_SET_RATE_PARENT from peripheral clocksJerome Brunet1-1/+1
On Amlogic SoCs, the rate of a peripheral clock should not be changed, let alone the rate of the parent PLL. These clocks are meant to be used as provided by the parent PLL. Changing the rate would be dangerous and would likely break a lot of devices running from the same PLL. Don't propagate any rate change request that may come from these clocks and drop the corresponding flag. Link: https://lore.kernel.org/r/20250825-meson-clk-cleanup-24-v2-6-0f402f01e117@baylibre.com Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2025-09-04clk: amlogic: move PCLK definition to clkc-utilsJerome Brunet2-20/+21
clk-regmap was always meant to stay generic, without any amlogic specifics. The hope was that it could move out of the amlogic directory one day. Even if this may actually not become true, it should remain generic. Move the amlogic peripheral clock definition out of clk-regmap header. Link: https://lore.kernel.org/r/20250825-meson-clk-cleanup-24-v2-5-0f402f01e117@baylibre.com Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2025-09-04clk: amlogic: aoclk: use clkc-utils syscon probeJerome Brunet5-31/+33
The clock related part of aoclk probe function duplicates what the clkc-utils syscon helper does. Factorize this to have a single path to maintain. Link: https://lore.kernel.org/r/20250825-meson-clk-cleanup-24-v2-4-0f402f01e117@baylibre.com Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2025-09-04clk: amlogic: use probe helper in mmio based controllersJerome Brunet7-304/+66
Factorize the probe function of the mmio based amlogic clock controllers using the newly introduced probe helper. This removes a fair amount of duplicated code. Reviewed-by: Chuan Liu <chuan.liu@amlogic.com> Link: https://lore.kernel.org/r/20250825-meson-clk-cleanup-24-v2-3-0f402f01e117@baylibre.com Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2025-09-04clk: amlogic: add probe helper for mmio based controllersJerome Brunet2-13/+50
Add a 2nd probe function helper for mmio based controllers, which are getting the memory region from a resource instead of a syscon. Link: https://lore.kernel.org/r/20250825-meson-clk-cleanup-24-v2-2-0f402f01e117@baylibre.com Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2025-09-04clk: amlogic: drop meson-clkceeJerome Brunet9-115/+85
What is being done by the Amlogic clock controller registration helper for EE controllers could benefit other controllers. As such, having a specific module for this makes little sense. Move the helper function to clkc-utils and rename it to describe what it does, registering syscon based controller, instead of what it serves. Link: https://lore.kernel.org/r/20250825-meson-clk-cleanup-24-v2-1-0f402f01e117@baylibre.com Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2025-08-25clk: amlogic: naming consistency alignmentJerome Brunet14-3620/+3563
Amlogic clock controller drivers are all doing the same thing, more or less. Yet, over the years, tiny (and often pointless) differences have emerged. This makes reviews more difficult, allows some errors to slip through and make it more difficult to exploit SoC commonalities, leading to code duplication. This change enforce, wherever possible, a consistent and predictable scheme when it comes to code organisation and naming, The scheme chosen is what was used the most already, to try and minimise the size of the ugly resulting diff. Here are some of the rules applied: - Aligning clock names, variable names and IDs. - ID cannot change (used in DT) - Variable names w/ SoC name prefixes - Clock names w/o SoC name prefixes, except pclks for historic reasons - Composite clock systematic naming : mux: X_sel, div:X_div, gate:X - Parent table systematically named with the same name as the clock and a '_parents' suffix - Group various tables next to the related clock - etc ... Doing so removes what would otherwise show up as unrelated diff in following changes. It will allow to introduce common definitions for peripheral clocks, probe helpers, composite clocks, etc ... making further review and maintenance easier. Link: https://lore.kernel.org/r/20250702-meson-clk-cleanup-24-v1-1-e163c9a1fc21@baylibre.com Link: https://lore.kernel.org/r/20250702-meson-clk-cleanup-24-v1-2-e163c9a1fc21@baylibre.com Link: https://lore.kernel.org/r/20250702-meson-clk-cleanup-24-v1-3-e163c9a1fc21@baylibre.com Link: https://lore.kernel.org/r/20250702-meson-clk-cleanup-24-v1-4-e163c9a1fc21@baylibre.com Link: https://lore.kernel.org/r/20250702-meson-clk-cleanup-24-v1-5-e163c9a1fc21@baylibre.com Link: https://lore.kernel.org/r/20250702-meson-clk-cleanup-24-v1-6-e163c9a1fc21@baylibre.com Link: https://lore.kernel.org/r/20250702-meson-clk-cleanup-24-v1-7-e163c9a1fc21@baylibre.com Link: https://lore.kernel.org/r/20250702-meson-clk-cleanup-24-v1-8-e163c9a1fc21@baylibre.com Link: https://lore.kernel.org/r/20250702-meson-clk-cleanup-24-v1-9-e163c9a1fc21@baylibre.com Link: https://lore.kernel.org/r/20250702-meson-clk-cleanup-24-v1-10-e163c9a1fc21@baylibre.com Link: https://lore.kernel.org/r/20250702-meson-clk-cleanup-24-v1-11-e163c9a1fc21@baylibre.com Link: https://lore.kernel.org/r/20250702-meson-clk-cleanup-24-v1-12-e163c9a1fc21@baylibre.com Link: https://lore.kernel.org/r/20250702-meson-clk-cleanup-24-v1-13-e163c9a1fc21@baylibre.com Link: https://lore.kernel.org/r/20250702-meson-clk-cleanup-24-v1-14-e163c9a1fc21@baylibre.com Reviewed-by: Chuan Liu <chuan.liu@amlogic.com> # For c3 and s4 [jbrunet: squashed all naming alignment changes together] Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2025-07-29Merge branches 'clk-renesas', 'clk-samsung', 'clk-spacemit', 'clk-allwinner' ↵Stephen Boyd39-3082/+639
and 'clk-amlogic' into clk-next * clk-renesas: (42 commits) clk: renesas: r9a08g045: Add MSTOP for coupled clocks as well clk: renesas: r9a09g047: Add clock and reset signals for the GBETH IPs clk: renesas: r9a09g057: Add XSPI clock/reset clk: renesas: r9a09g056: Add XSPI clock/reset clk: renesas: rzv2h: Add fixed-factor module clocks with status reporting clk: renesas: r9a09g057: Add support for xspi mux and divider clk: renesas: r9a09g056: Add support for xspi mux and divider clk: renesas: r9a09g077: Add RIIC module clocks clk: renesas: r9a09g077: Add PLL2 and SDHI clock support clk: renesas: rzv2h: Drop redundant base pointer from pll_clk clk: renesas: r9a09g057: Add entries for the RSPIs dt-bindings: clock: renesas,r9a09g077/87: Add SDHI_CLKHS clock ID dt-bindings: clock: renesas,r9a09g056/57-cpg: Add XSPI core clock clk: renesas: rzv2h: Add missing include file clk: renesas: rzv2h: Use devm_kmemdup_array() clk: renesas: Add CPG/MSSR support to RZ/N2H SoC clk: renesas: r9a09g077: Add PCLKL core clock dt-bindings: clock: renesas,cpg-mssr: Document RZ/N2H support dt-bindings: soc: renesas: Document RZ/N2H (R9A09G087) SoC dt-bindings: clock: renesas,r9a09g077: Add PCLKL core clock ID ... * clk-samsung: clk: samsung: exynosautov920: add block hsi2 clock support dt-bindings: clock: exynosautov920: add hsi2 clock definitions dt-bindings: clock: exynosautov920: sort clock definitions clk: samsung: exynos850: fix a comment clk: samsung: gs101: fix alternate mout_hsi0_usb20_ref parent clock clk: samsung: gs101: fix CLK_DOUT_CMU_G3D_BUSD * clk-spacemit: clk: spacemit: ccu_pll: fix error return value in recalc_rate callback reset: spacemit: add support for SpacemiT CCU resets clk: spacemit: mark K1 pll1_d8 as critical clk: spacemit: define three reset-only CCUs clk: spacemit: set up reset auxiliary devices soc: spacemit: create a header for clock/reset registers dt-bindings: soc: spacemit: define spacemit,k1-ccu resets * clk-allwinner: clk: sunxi-ng: ccu_nm: convert from round_rate() to determine_rate() clk: sunxi-ng: ccu_nkmp: convert from round_rate() to determine_rate() clk: sunxi-ng: ccu_nk: convert from round_rate() to determine_rate() clk: sunxi-ng: ccu_gate: convert from round_rate() to determine_rate() clk: sunxi-ng: v3s: Assign the de and tcon clocks to the video pll clk: sunxi-ng: v3s: Fix de clock definition clk: sunxi-ng: sun55i-a523-r-ccu: Add missing PPU0 reset dt-bindings: reset: sun55i-a523-r-ccu: Add missing PPU0 reset * clk-amlogic: clk: amlogic: s4: remove unused data clk: amlogic: drop clk_regmap tables clk: amlogic: get regmap with clk_regmap_init clk: amlogic: remove unnecessary headers clk: amlogic: axg-audio: use the auxiliary reset driver
2025-07-26clk: Fix typosBjorn Helgaas3-5/+5
Fix typos, mostly in comments except CLKGATE_SEPERATED_* (definition and uses updated). Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Link: https://lore.kernel.org/r/20250723203819.2910289-1-helgaas@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2025-07-02clk: amlogic: s4: remove unused dataJerome Brunet1-112/+0
Following the removal of the clk_regmap clock table from the s4-peripherals clock controller driver, it appears some clocks are unused, which means these are not exported or even registered. In all likelihood, these clocks have not been tested. Remove the unused clocks for now. These can added back later when they have been properly tested. Reviewed-by: Chuan Liu <chuan.liu@amlogic.com> Link: https://lore.kernel.org/r/20250623-amlogic-clk-drop-clk-regmap-tables-v4-3-ff04918211cc@baylibre.com Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2025-07-02clk: amlogic: drop clk_regmap tablesJerome Brunet19-2191/+5
Remove the clk_regmap tables that are used to keep track which clock need to be initialised before being registered. The initialisation is now done by the .init() operation of clk_regmap. This rework saves a bit memory and makes maintenance a bit easier. Link: https://lore.kernel.org/r/20250623-amlogic-clk-drop-clk-regmap-tables-v4-2-ff04918211cc@baylibre.com Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2025-07-02clk: amlogic: get regmap with clk_regmap_initJerome Brunet11-0/+89
Add clk_regmap_init() and use it with all clock types which derive from clk_regmap. This helps initialise clk_regmap clocks without requiring tables to keep track of the clock using this type. The way it is done couples clk_regmap with the controllers, which is not ideal. This is a temporary solution to get rid of the tables. The situation will eventually be improved. Link: https://lore.kernel.org/r/20250623-amlogic-clk-drop-clk-regmap-tables-v4-1-ff04918211cc@baylibre.com Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2025-06-30clk: amlogic: remove unnecessary headersJerome Brunet18-677/+530
Some Amlogic clock controller drivers have a dedicated headers file, some do not. Over time, these headers have evolved and now only carry register offset definitions. These offsets are only used by the related controller and are not meant to be shared. These headers are not serving any purpose now. Start enforcing some consistency between the different Amlogic clock drivers and move the register offset definitions to the related driver. Link: https://lore.kernel.org/r/20250623-clk-meson-no-headers-v1-1-468161a7279e@baylibre.com [jbrunet: checkpatch strict: removed extra blank line] Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2025-06-23clk: amlogic: axg-audio: use the auxiliary reset driverJerome Brunet2-102/+15
Remove the implementation of the reset driver in axg audio clock driver and migrate to the one provided by reset framework on the auxiliary bus. Link: https://lore.kernel.org/r/20250611-clk-aux-v1-4-fb6575ed86a7@baylibre.com Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2025-05-15clk: meson: Do not enable by default during compile testingKrzysztof Kozlowski1-8/+8
Enabling the compile test should not cause automatic enabling of all drivers. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Link: https://lore.kernel.org/r/20250404-kconfig-defaults-clk-v1-1-4d2df5603332@linaro.org Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2025-05-15clk: meson-g12a: add missing fclk_div2 to spiccDa Xue1-0/+1
SPICC is missing fclk_div2, which means fclk_div5 and fclk_div7 indexes are wrong on this clock. This causes the spicc module to output sclk at 2.5x the expected rate when clock index 3 is picked. Adding the missing fclk_div2 resolves this. [jbrunet: amended commit description] Fixes: a18c8e0b7697 ("clk: meson: g12a: add support for the SPICC SCLK Source clocks") Cc: stable@vger.kernel.org # 6.1 Signed-off-by: Da Xue <da@libre.computer> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Link: https://lore.kernel.org/r/20250512142617.2175291-1-da@libre.computer Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2025-03-14clk: amlogic: a1: fix a typoJian Hu1-1/+1
Fix a typo in MODULE_DESCRIPTION for a1 PLL driver, S4 should be A1. Signed-off-by: Jian Hu <jian.hu@amlogic.com> Reviewed-by: Dmitry Rokosov <ddrokosov@salutedevices.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20241231062552.2982266-1-jian.hu@amlogic.com Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2025-03-14clk: amlogic: gxbb: drop non existing 32k clock parentJerome Brunet1-6/+6
The 32k clock reference a parent 'cts_slow_oscin' with a fixme note saying that this clock should be provided by AO controller. The HW probably has this clock but it does not exist at the moment in any controller implementation. Furthermore, referencing clock by the global name should be avoided whenever possible. There is no reason to keep this hack around, at least for now. Fixes: 14c735c8e308 ("clk: meson-gxbb: Add EE 32K Clock for CEC") Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20241220-amlogic-clk-gxbb-32k-fixes-v1-2-baca56ecf2db@baylibre.com Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2025-03-14clk: amlogic: gxbb: drop incorrect flag on 32k clockJerome Brunet1-1/+1
gxbb_32k_clk_div sets CLK_DIVIDER_ROUND_CLOSEST in the init_data flag which is incorrect. This is field is not where the divider flags belong. Thankfully, CLK_DIVIDER_ROUND_CLOSEST maps to bit 4 which is an unused clock flag, so there is no unintended consequence to this error. Effectively, the clock has been used without CLK_DIVIDER_ROUND_CLOSEST so far, so just drop it. Fixes: 14c735c8e308 ("clk: meson-gxbb: Add EE 32K Clock for CEC") Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20241220-amlogic-clk-gxbb-32k-fixes-v1-1-baca56ecf2db@baylibre.com Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2025-03-14clk: amlogic: g12b: fix cluster A parent dataJerome Brunet1-12/+24
Several clocks used by both g12a and g12b use the g12a cpu A clock hw pointer as clock parent. This is incorrect on g12b since the parents of cluster A cpu clock are different. Also the hw clock provided as parent to these children is not even registered clock on g12b. Fix the problem by reverting to the global namespace and let CCF pick the appropriate, as it is already done for other clocks, such as cpu_clk_trace_div. Fixes: 25e682a02d91 ("clk: meson: g12a: migrate to the new parent description method") Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20241213-amlogic-clk-g12a-cpua-parent-fix-v1-1-d8c0f41865fe@baylibre.com Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2025-03-14clk: amlogic: g12a: fix mmc A peripheral clockJerome Brunet1-1/+1
The bit index of the peripheral clock for mmc A is wrong This was probably not a problem for mmc A as the peripheral is likely left enabled by the bootloader. No issues has been reported so far but it could be a problem, most likely some form of conflict between the ethernet and mmc A clock, breaking ethernet on init. Use the value provided by the documentation for mmc A before this becomes an actual problem. Fixes: 085a4ea93d54 ("clk: meson: g12a: add peripheral clock controller") Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20241213-amlogic-clk-g12a-mmca-fix-v1-1-5af421f58b64@baylibre.com Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2024-12-10Merge tag 'clk-fixes-for-linus' of ↵Linus Torvalds2-10/+101
git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk fixes from Stephen Boyd: "Two reverts and two EN7581 driver fixes: - Revert the attempt to make CLK_GET_RATE_NOCACHE flag work in clk_set_rate() because it led to problems with the Qualcomm CPUFreq driver - Revert Amlogic reset driver back to the initial implementation. This broke probe of the audio subsystem on axg based platforms and also had compilation problems. We'll try again next time. - Fix a clk frequency and fix array bounds runtime checks in the Airoha EN7581 driver" * tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: clk: en7523: Initialize num before accessing hws in en7523_register_clocks() clk: en7523: Fix wrong BUS clock for EN7581 clk: amlogic: axg-audio: revert reset implementation Revert "clk: Fix invalid execution of clk_set_rate"
2024-12-02clk: amlogic: axg-audio: revert reset implementationJerome Brunet2-10/+101
The audio subsystem of axg based platform is not probing anymore. This is due to the introduction of RESET_MESON_AUX and the config not being enabled with the default arm64 defconfig. This brought another discussion around proper decoupling between the clock and reset part. While this discussion gets sorted out, revert back to the initial implementation. This reverts * commit 681ed497d676 ("clk: amlogic: axg-audio: fix Kconfig dependency on RESET_MESON_AUX") * commit 664988eb47dd ("clk: amlogic: axg-audio: use the auxiliary reset driver") Both are reverted with single change to avoid creating more compilation problems. Fixes: 681ed497d676 ("clk: amlogic: axg-audio: fix Kconfig dependency on RESET_MESON_AUX") Cc: Arnd Bergmann <arnd@arndb.de> Reported-by: Mark Brown <broonie@kernel.org> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Link: https://lore.kernel.org/r/20241128-clk-audio-fix-rst-missing-v2-1-cf437d1a73da@baylibre.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-12-02module: Convert symbol namespace to string literalPeter Zijlstra25-49/+49
Clean up the existing export namespace code along the same lines of commit 33def8498fdd ("treewide: Convert macro and uses of __section(foo) to __section("foo")") and for the same reason, it is not desired for the namespace argument to be a macro expansion itself. Scripted using git grep -l -e MODULE_IMPORT_NS -e EXPORT_SYMBOL_NS | while read file; do awk -i inplace ' /^#define EXPORT_SYMBOL_NS/ { gsub(/__stringify\(ns\)/, "ns"); print; next; } /^#define MODULE_IMPORT_NS/ { gsub(/__stringify\(ns\)/, "ns"); print; next; } /MODULE_IMPORT_NS/ { $0 = gensub(/MODULE_IMPORT_NS\(([^)]*)\)/, "MODULE_IMPORT_NS(\"\\1\")", "g"); } /EXPORT_SYMBOL_NS/ { if ($0 ~ /(EXPORT_SYMBOL_NS[^(]*)\(([^,]+),/) { if ($0 !~ /(EXPORT_SYMBOL_NS[^(]*)\(([^,]+), ([^)]+)\)/ && $0 !~ /(EXPORT_SYMBOL_NS[^(]*)\(\)/ && $0 !~ /^my/) { getline line; gsub(/[[:space:]]*\\$/, ""); gsub(/[[:space:]]/, "", line); $0 = $0 " " line; } $0 = gensub(/(EXPORT_SYMBOL_NS[^(]*)\(([^,]+), ([^)]+)\)/, "\\1(\\2, \"\\3\")", "g"); } } { print }' $file; done Requested-by: Masahiro Yamada <masahiroy@kernel.org> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://mail.google.com/mail/u/2/#inbox/FMfcgzQXKWgMmjdFwwdsfgxzKpVHWPlc Acked-by: Greg KH <gregkh@linuxfoundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2024-11-14clk: amlogic: axg-audio: fix Kconfig dependency on RESET_MESON_AUXArnd Bergmann1-1/+1
As in most cases, using 'imply' is wrong here and does not prevent build failures since that code may not be visible to a built-in clk driver: axg-audio.c:(.text+0x15c): undefined reference to `devm_meson_rst_aux_register' Replace the incorrt 'imply' with the necessary 'depends on'. Fixes: 664988eb47dd ("clk: amlogic: axg-audio: use the auxiliary reset driver") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Link: https://lore.kernel.org/r/20241111102932.3209861-1-arnd@kernel.org Reviewed-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-10-14clk: amlogic: axg-audio: use the auxiliary reset driverJerome Brunet2-100/+10
Remove the implementation of the reset driver in axg audio clock driver and migrate to the one provided by the reset framework on the auxiliary bus Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20241008-meson-clk-rst-aux-v2-1-682ab9151f4f@baylibre.com Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2024-09-30clk: meson: meson8b: remove spinlockJerome Brunet1-7/+0
The spinlock in meson8b clock controller is now only protecting a call to regmap_update_bits(). The regmap API already has its own locking system so this spinlock is redundant. Remove it. Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Link: https://lore.kernel.org/r/20240925-clk-meson8b-spinlock-v1-1-50b7f2d02d7d@baylibre.com [jbrunet: amended to remove unused variable as reported by lkp] Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2024-09-30clk: meson: mpll: Delete a useless spinlock from the MPLLChuan Liu7-39/+0
The register corresponding to MPLL does not share the same register with other module drivers, so there is no concurrent access to the register with other modules drivers. The spinlock defined in struct meson_clk_mpll_data is no longer useful. Signed-off-by: Chuan Liu <chuan.liu@amlogic.com> Link: https://lore.kernel.org/r/20240925-mpll_spinlock-v2-1-8f9b73588ec1@amlogic.com Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2024-09-30clk: meson: s4: pll: fix frac maximum value for hifi_pllChuan Liu1-0/+1
The fractional denominator of S4's hifi_pll fractional multiplier is fixed to 100000. Fixes: 80344f4c1a1e ("clk: meson: s4: pll: hifi_pll support fractional multiplier") Signed-off-by: Chuan Liu <chuan.liu@amlogic.com> Link: https://lore.kernel.org/r/20240909-fix_clk-v3-3-a6d8f6333c04@amlogic.com Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2024-09-30clk: meson: c3: pll: fix frac maximum value for hifi_pllChuan Liu1-0/+1
The fractional denominator of C3's hifi_pll fractional multiplier is fixed to 100000. Fixes: 8a9a129dc565 ("clk: meson: c3: add support for the C3 SoC PLL clock") Signed-off-by: Chuan Liu <chuan.liu@amlogic.com> Link: https://lore.kernel.org/r/20240909-fix_clk-v3-2-a6d8f6333c04@amlogic.com Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2024-09-30clk: meson: Support PLL with fixed fractional denominatorsChuan Liu2-3/+6
Some PLLS with fractional multipliers have fractional denominators with fixed values, instead of the previous "(1 << pll-> frc.width)". Signed-off-by: Chuan Liu <chuan.liu@amlogic.com> Link: https://lore.kernel.org/r/20240909-fix_clk-v3-1-a6d8f6333c04@amlogic.com Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2024-09-30clk: meson: s4: pll: hifi_pll support fractional multiplierChuan Liu1-1/+5
The s4's hifi_pll supports a fractional frequency multiplier, but frac parameters are not configured in the driver. Signed-off-by: Chuan Liu <chuan.liu@amlogic.com> Link: https://lore.kernel.org/r/20240906-fix_clk-v1-3-2977ef0d72e7@amlogic.com Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2024-07-29clk: meson: introduce symbol namespace for amlogic clocksJerome Brunet25-25/+49
Symbols exported by the Amlogic clock modules are only meant to be used by Amlogic clock controller drivers. Using a dedicated symbols namespace make that clear and help clean the global namespace of symbols other modules do no need. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20240719094228.3985595-1-jbrunet@baylibre.com Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2024-07-29clk: meson: axg-audio: add sm1 earcrx clocksJerome Brunet2-1/+33
Add CMDC, DMAC and peripheral clocks for the eARC RX device found on the sm1 SoC family Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20240719093934.3985139-4-jbrunet@baylibre.com Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2024-07-29clk: meson: axg-audio: setup regmap max_register based on the SoCJerome Brunet1-2/+6
The register region of axg-audio tends to grow with the addition of new supported SoC. Mapping slightly more has not been causing problem so far but it is not viable to continue like this long term. Setup the max register based on what is necessary on the related SoC. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20240719093934.3985139-3-jbrunet@baylibre.com Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2024-07-10clk: meson: s4: pll: Constify struct regmap_configJavier Carrasco1-1/+1
`clkc_regmap_config` is not modified and can be declared as const to move its data to a read-only section. Signed-off-by: Javier Carrasco <javier.carrasco.cruz@gmail.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20240703-clk-const-regmap-v1-6-7d15a0671d6f@gmail.com Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2024-07-10clk: meson: s4: peripherals: Constify struct regmap_configJavier Carrasco1-1/+1
`clkc_regmap_config` is not modified and can be declared as const to move its data to a read-only section. Signed-off-by: Javier Carrasco <javier.carrasco.cruz@gmail.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20240703-clk-const-regmap-v1-5-7d15a0671d6f@gmail.com Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2024-07-10clk: meson: c3: pll: Constify struct regmap_configJavier Carrasco1-1/+1
`clkc_regmap_config` is not modified and can be declared as const to move its data to a read-only section. Signed-off-by: Javier Carrasco <javier.carrasco.cruz@gmail.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20240703-clk-const-regmap-v1-4-7d15a0671d6f@gmail.com Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2024-07-10clk: meson: c3: peripherals: Constify struct regmap_configJavier Carrasco1-1/+1
`clkc_regmap_config` is not modified and can be declared as const to move its data to a read-only section. Signed-off-by: Javier Carrasco <javier.carrasco.cruz@gmail.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20240703-clk-const-regmap-v1-3-7d15a0671d6f@gmail.com Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2024-07-10clk: meson: a1: pll: Constify struct regmap_configJavier Carrasco1-1/+1
`a1_pll_regmap_cfg` is not modified and can be declared as const to move its data to a read-only section. Signed-off-by: Javier Carrasco <javier.carrasco.cruz@gmail.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20240703-clk-const-regmap-v1-2-7d15a0671d6f@gmail.com Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2024-07-10clk: meson: a1: peripherals: Constify struct regmap_configJavier Carrasco1-1/+1
`a1_periphs_regmap_cfg` is not modified and can be declared as const to move its data to a read-only section. Signed-off-by: Javier Carrasco <javier.carrasco.cruz@gmail.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20240703-clk-const-regmap-v1-1-7d15a0671d6f@gmail.com Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2024-06-14clk: meson: add missing MODULE_DESCRIPTION() macrosJerome Brunet15-11/+29
Add the missing MODULE_DESCRIPTION() in the Amlogic clock modules missing it. Reported-by: Jeff Johnson <quic_jjohnson@quicinc.com> Closes: https://lore.kernel.org/linux-clk/964210f1-671f-4ecc-bdb7-3cf53089c327@quicinc.com Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20240611133512.341817-1-jbrunet@baylibre.com Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2024-06-10clk: meson: add 'NOINIT_ENABLED' flag to eliminate init for enabled PLLDmitry Rokosov2-16/+25
When dealing with certain PLLs, it is necessary to avoid modifying them if they have already been initialized by lower levels. For instance, in the A1 SoC Family, the sys_pll is enabled as the parent for the cpuclk, and it cannot be disabled during the initialization sequence. Therefore, initialization phase must be skipped. Signed-off-by: Dmitry Rokosov <ddrokosov@salutedevices.com> Link: https://lore.kernel.org/r/20240515185103.20256-2-ddrokosov@salutedevices.com Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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