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8 daysMerge tag 'dmaengine-7.1-rc1' of ↵Linus Torvalds-376/+3292
git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine Pull dmaengine updates from Vinod Koul: "Core: - New devm_of_dma_controller_register() API New Support: - Support for RZ/G3L SoC - Loongson Multi-Channel DMA controller support - Conversion of Xilinx AXI DMA binding - DW AXI CV1800B DMA support - Switchtec DMA engine driver Updates: - AMD MDB Endpoint and non-LL mode support - DW edma virtual IRQ for interrupt-emulation, cyclic transfers support" * tag 'dmaengine-7.1-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine: (65 commits) dmaengine: dw-edma: Add non-LL mode dmaengine: dw-edma: Add AMD MDB Endpoint Support dt-bindings: dmaengine: Fix spelling mistake "Looongson" -> "Looogson" dmaengine: loongson: Fix spelling mistake "Looongson" -> "Looogson" dmaengine: loongson: New driver for the Loongson Multi-Channel DMA controller dt-bindings: dmaengine: Add Loongson Multi-Channel DMA controller dmaengine: loongson: loongson2-apb: Simplify locking with guard() and scoped_guard() dmaengine: loongson: loongson2-apb: Convert to devm_clk_get_enabled() dmaengine: loongson: loongson2-apb: Convert to dmaenginem_async_device_register() dmaengine: loongson: New directory for Loongson DMA controllers drivers dt-bindings: dma: xlnx,axi-dma: Convert to DT schema dt-bindings: dma: rz-dmac: Add conditional schema for RZ/G3L dmaengine: sh: rz-dmac: Add device_{pause,resume}() callbacks dmaengine: sh: rz-dmac: Add device_tx_status() callback dmaengine: sh: rz-dmac: Use rz_lmdesc_setup() to invalidate descriptors dmaengine: sh: rz-dmac: Drop unnecessary local_irq_save() call dmaengine: sh: rz-dmac: Drop goto instruction and label dmaengine: sh: rz-dmac: Drop read of CHCTRL register dmaengine: sh: rz_dmac: add RZ/{T2H,N2H} support dt-bindings: dma: renesas,rz-dmac: document RZ/{T2H,N2H} ...
2026-03-18dmaengine: dw-edma: Add non-LL modeDevendra K Verma-15/+142
AMD MDB IP supports Linked List (LL) mode as well as non-LL mode. The current code does not have the mechanisms to enable the DMA transactions using the non-LL mode. The following two cases are added with this patch: - For the AMD (Xilinx) only, when a valid physical base address of the device side DDR is not configured, then the IP can still be used in non-LL mode. For all the channels DMA transactions will be using the non-LL mode only. This, the default non-LL mode, is not applicable for Synopsys IP with the current code addition. - If the default mode is LL-mode, for both AMD (Xilinx) and Synosys, and if user wants to use non-LL mode then user can do so via configuring the peripheral_config param of dma_slave_config. Signed-off-by: Devendra K Verma <devendra.verma@amd.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/20260318070403.1634706-3-devendra.verma@amd.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-03-18dmaengine: dw-edma: Add AMD MDB Endpoint SupportDevendra K Verma-14/+176
AMD MDB PCIe endpoint support. For AMD specific support added the following - AMD supported PCIe Device IDs and Vendor ID (Xilinx). - AMD MDB specific driver data - AMD MDB specific VSEC capability to retrieve the device DDR base address. Signed-off-by: Devendra K Verma <devendra.verma@amd.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/20260318070403.1634706-2-devendra.verma@amd.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-03-18dmaengine: loongson: Fix spelling mistake "Looongson" -> "Looogson"Colin Ian King-2/+2
There are a couple of spelling mistakes, one in a comment block and one in a module description. Fix them. Signed-off-by: Colin Ian King <colin.i.king@gmail.com> Link: https://patch.msgid.link/20260317204631.120332-1-colin.i.king@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-03-17dmaengine: loongson: New driver for the Loongson Multi-Channel DMA controllerBinbin Zhou-0/+742
This DMA controller appears in Loongson-2K0300 and Loongson-2K3000. It is a chain multi-channel controller that enables data transfers from memory to memory, device to memory, and memory to device, as well as channel prioritization configurable through the channel configuration registers. In addition, there are slight differences between Loongson-2K0300 and Loongson-2K3000, such as channel register offsets and the number of channels. Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn> Reviewed-by: Huacai Chen <chenhuacai@loongson.cn> Link: https://patch.msgid.link/73bc32ba6249f1eef94fec9b349bc9efa98278ea.1772853681.git.zhoubinbin@loongson.cn Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-03-17dmaengine: loongson: loongson2-apb: Simplify locking with guard() and ↵Binbin Zhou-33/+29
scoped_guard() Use guard() and scoped_guard() infrastructure instead of explicitly acquiring and releasing spinlocks to simplify the code and ensure that all locks are released properly. Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn> Reviewed-by: Huacai Chen <chenhuacai@loongson.cn> Link: https://patch.msgid.link/fb59bb25e5c4fcb84d9aa7b351285fa8d02ea8cb.1772853681.git.zhoubinbin@loongson.cn Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-03-17dmaengine: loongson: loongson2-apb: Convert to devm_clk_get_enabled()Binbin Zhou-17/+5
Use the devm_clk_get_enabled() helper function to simplify the probe routine. Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn> Reviewed-by: Huacai Chen <chenhuacai@loongson.cn> Link: https://patch.msgid.link/4f3aad22d14e730cc040ece8b0ced37853d52876.1772853681.git.zhoubinbin@loongson.cn Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-03-17dmaengine: loongson: loongson2-apb: Convert to ↵Binbin Zhou-5/+2
dmaenginem_async_device_register() Use the dmaenginem_async_device_register() helper function to simplify the probe routine. Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn> Reviewed-by: Huacai Chen <chenhuacai@loongson.cn> Link: https://patch.msgid.link/c56e67ecde38e9a3bda5f88ea3fc20b97a5cba6c.1772853681.git.zhoubinbin@loongson.cn Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-03-17dmaengine: loongson: New directory for Loongson DMA controllers driversBinbin Zhou-29/+40
Gather the Loongson DMA controllers under drivers/dma/loongson/ Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn> Reviewed-by: Keguang Zhang <keguang.zhang@gmail.com> Reviewed-by: Huacai Chen <chenhuacai@loongson.cn> Link: https://patch.msgid.link/0a0853a85630724741061f6fe08680610e49a06e.1772853681.git.zhoubinbin@loongson.cn Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-03-17dmaengine: xilinx_dma: Fix reset related timeout with two-channel AXIDMATomi Valkeinen-8/+1
A single AXIDMA controller can have one or two channels. When it has two channels, the reset for both are tied together: resetting one channel resets the other as well. This creates a problem where resetting one channel will reset the registers for both channels, including clearing interrupt enable bits for the other channel, which can then lead to timeouts as the driver is waiting for an interrupt which never comes. The driver currently has a probe-time work around for this: when a channel is created, the driver also resets and enables the interrupts. With two channels the reset for the second channel will clear the interrupt enables for the first one. The work around in the driver is just to manually enable the interrupts again in xilinx_dma_alloc_chan_resources(). This workaround only addresses the probe-time issue. When channels are reset at runtime (e.g., in xilinx_dma_terminate_all() or during error recovery), there's no corresponding mechanism to restore the other channel's interrupt enables. This leads to one channel having its interrupts disabled while the driver expects them to work, causing timeouts and DMA failures. A proper fix is a complicated matter, as we should not reset the other channel when it's operating normally. So, perhaps, there should be some kind of synchronization for a common reset, which is not trivial to implement. To add to the complexity, the driver also supports other DMA types, like VDMA, CDMA and MCDMA, which don't have a shared reset. However, when the two-channel AXIDMA is used in the (assumably) normal use case, providing DMA for a single memory-to-memory device, the common reset is a bit smaller issue: when something bad happens on one channel, or when one channel is terminated, the assumption is that we also want to terminate the other channel. And thus resetting both at the same time is "ok". With that line of thinking we can implement a bit better work around than just the current probe time work around: let's enable the AXIDMA interrupts at xilinx_dma_start_transfer() instead. This ensures interrupts are enabled whenever a transfer starts, regardless of any prior resets that may have cleared them. This approach is also more logical: enable interrupts only when needed for a transfer, rather than at resource allocation time, and, I think, all the other DMA types should also use this model, but I'm reluctant to do such changes as I cannot test them. The reset function still enables interrupts even though it's not needed for AXIDMA anymore, but it's common code for all DMA types (VDMA, CDMA, MCDMA), so leave it unchanged to avoid affecting other variants. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com> Fixes: c0bba3a99f07 ("dmaengine: vdma: Add Support for Xilinx AXI Direct Memory Access Engine") Link: https://patch.msgid.link/20260311-xilinx-dma-fix-v2-1-a725abb66e3c@ideasonboard.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-03-17dmaengine: xilinx: xilinx_dma: Fix unmasked residue subtractionMarek Vasut-6/+6
The segment .control and .status fields both contain top bits which are not part of the buffer size, the buffer size is located only in the bottom max_buffer_len bits. To avoid interference from those top bits, mask out the size using max_buffer_len first, and only then subtract the values. Fixes: a575d0b4e663 ("dmaengine: xilinx_dma: Introduce xilinx_dma_get_residue") Signed-off-by: Marek Vasut <marex@nabladev.com> Link: https://patch.msgid.link/20260316222530.163815-1-marex@nabladev.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-03-17dmaengine: xilinx: xilinx_dma: Fix residue calculation for cyclic DMAMarek Vasut-1/+22
The cyclic DMA calculation is currently entirely broken and reports residue only for the first segment. The problem is twofold. First, when the first descriptor finishes, it is moved from active_list to done_list, but it is never returned back into the active_list. The xilinx_dma_tx_status() expects the descriptor to be in the active_list to report any meaningful residue information, which never happens after the first descriptor finishes. Fix this up in xilinx_dma_start_transfer() and if the descriptor is cyclic, lift it from done_list and place it back into active_list list. Second, the segment .status fields of the descriptor remain dirty. Once the DMA did one pass on the descriptor, the .status fields are populated with data by the DMA, but the .status fields are not cleared before reuse during the next cyclic DMA round. The xilinx_dma_get_residue() recognizes that as if the descriptor was complete and had 0 residue, which is bogus. Reinitialize the status field before placing the descriptor back into the active_list. Fixes: c0bba3a99f07 ("dmaengine: vdma: Add Support for Xilinx AXI Direct Memory Access Engine") Signed-off-by: Marek Vasut <marex@nabladev.com> Link: https://patch.msgid.link/20260316221943.160375-1-marex@nabladev.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-03-17dmaengine: xilinx: xilinx_dma: Fix dma_device directionsMarek Vasut-1/+1
Unlike chan->direction , struct dma_device .directions field is a bitfield. Turn chan->direction into a bitfield to make it compatible with struct dma_device .directions . Fixes: 7e01511443c3 ("dmaengine: xilinx_dma: Set dma_device directions") Signed-off-by: Marek Vasut <marex@nabladev.com> Link: https://patch.msgid.link/20260316221728.160139-1-marex@nabladev.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-03-17dmaengine: sh: rz-dmac: Add device_{pause,resume}() callbacksClaudiu Beznea-3/+46
The RZ/G2L SCIFA driver uses dmaengine_prep_slave_sg() to enqueue DMA transfers and implements a timeout mechanism on RX to handle cases where a DMA transfer does not complete. The timeout is implemented using an hrtimer. In the hrtimer callback, dmaengine_tx_status() is called (along with dmaengine_pause()) to retrieve the transfer residue and handle incomplete DMA transfers. Add support for device_{pause, resume}() callbacks. Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Link: https://patch.msgid.link/20260316133252.240348-9-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-03-17dmaengine: sh: rz-dmac: Add device_tx_status() callbackBiju Das-1/+143
The RZ/G2L SCIFA driver uses dmaengine_prep_slave_sg() to enqueue DMA transfers and implements a timeout mechanism on RX to handle cases where a DMA transfer does not complete. The timeout is implemented using an hrtimer. In the hrtimer callback, dmaengine_tx_status() is called (along with dmaengine_pause()) to retrieve the transfer residue and handle incomplete DMA transfers. Add support for the device_tx_status() callback. Co-developed-by: Long Luu <long.luu.ur@renesas.com> Signed-off-by: Long Luu <long.luu.ur@renesas.com> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Co-developed-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/20260316133252.240348-8-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-03-17dmaengine: sh: rz-dmac: Use rz_lmdesc_setup() to invalidate descriptorsJohn Madieu-8/+2
rz_lmdesc_setup() invalidates DMA descriptors more comprehensively. It resets the base, head, and tail pointers of the descriptor list and clears the descriptor headers and their NXLA pointers. Use rz_lmdesc_setup() instead of open-coding parts of its logic. Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/20260316133252.240348-7-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-03-17dmaengine: sh: rz-dmac: Drop unnecessary local_irq_save() callClaudiu Beznea-5/+0
rz_dmac_enable_hw() calls local_irq_save()/local_irq_restore(), but this is not needed because the callers of rz_dmac_enable_hw() already protect the critical section using spin_lock_irqsave()/spin_lock_irqrestore(). Remove the local_irq_save()/local_irq_restore() calls. Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Link: https://patch.msgid.link/20260316133252.240348-6-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-03-17dmaengine: sh: rz-dmac: Drop goto instruction and labelClaudiu Beznea-3/+1
There is no need to jump to the done label, so return immediately. Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Link: https://patch.msgid.link/20260316133252.240348-5-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-03-17dmaengine: sh: rz-dmac: Drop read of CHCTRL registerClaudiu Beznea-3/+6
The CHCTRL register has 11 bits that can be updated by software. The documentation for all these bits states the following: - A read operation results in 0 being read - Writing zero does not affect the operation All bits in the CHCTRL register accessible by software are set and clear bits. The documentation for the CLREND bit of CHCTRL states: Setting this bit to 1 can clear the END bit of the CHSTAT_n/nS register. Also, the DMA transfer end interrupt is cleared. An attempt to read this bit results in 0 being read. 1: Clears the END bit. 0: Does not affect the operation. Since writing zero to any bit in this register does not affect controller operation and reads always return zero, there is no need to perform read-modify-write accesses to set the CLREND bit. Drop the read of the CHCTRL register. Also, since setting the CLREND bit does not interact with other functionalities exposed through this register and only clears the END interrupt, there is no need to lock around this operation. Add a comment to document this. Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Link: https://patch.msgid.link/20260316133252.240348-4-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-03-17Merge branch 'fixes' into nextVinod Koul-78/+137
This brings in the rz-dmac fixes which are in fixes
2026-03-17dmaengine: sh: rz-dmac: Move CHCTRL updates under spinlockClaudiu Beznea-5/+4
Both rz_dmac_disable_hw() and rz_dmac_irq_handle_channel() update the CHCTRL register. To avoid concurrency issues when configuring functionalities exposed by this registers, take the virtual channel lock. All other CHCTRL updates were already protected by the same lock. Previously, rz_dmac_disable_hw() disabled and re-enabled local IRQs, before accessing CHCTRL registers but this does not ensure race-free access. Remove the local IRQ disable/enable code as well. Fixes: 5000d37042a6 ("dmaengine: sh: Add DMAC driver for RZ/G2L SoC") Cc: stable@vger.kernel.org Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Link: https://patch.msgid.link/20260316133252.240348-3-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-03-17dmaengine: sh: rz-dmac: Protect the driver specific listsClaudiu Beznea-25/+32
The driver lists (ld_free, ld_queue) are used in rz_dmac_free_chan_resources(), rz_dmac_terminate_all(), rz_dmac_issue_pending(), and rz_dmac_irq_handler_thread(), all under the virtual channel lock. Take the same lock in rz_dmac_prep_slave_sg() and rz_dmac_prep_dma_memcpy() as well to avoid concurrency issues, since these functions also check whether the lists are empty and update or remove list entries. Fixes: 5000d37042a6 ("dmaengine: sh: Add DMAC driver for RZ/G2L SoC") Cc: stable@vger.kernel.org Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Link: https://patch.msgid.link/20260316133252.240348-2-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-03-09dmaengine: idxd: fix possible wrong descriptor completion in llist_abort_desc()Tuo Li-1/+1
At the end of this function, d is the traversal cursor of flist, but the code completes found instead. This can lead to issues such as NULL pointer dereferences, double completion, or descriptor leaks. Fix this by completing d instead of found in the final list_for_each_entry_safe() loop. Fixes: aa8d18becc0c ("dmaengine: idxd: add callback support for iaa crypto") Signed-off-by: Tuo Li <islituo@gmail.com> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Link: https://patch.msgid.link/20260106032428.162445-1-islituo@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-03-09dmaengine: sh: rz_dmac: add RZ/{T2H,N2H} supportCosmin Tanislav-0/+7
The Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs use a completely different ICU unit compared to RZ/V2H, which requires a separate implementation. Add support for them. RZ/N2H will use RZ/T2H as a fallback. Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260105114445.878262-5-cosmin-gabriel.tanislav.xa@renesas.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-03-09dmaengine: sh: rz_dmac: make register_dma_req() chip-specificCosmin Tanislav-29/+36
The Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs use a completely different ICU unit compared to RZ/V2H, which requires a separate implementation. To prepare for adding support for these SoCs, add a chip-specific structure and put a pointer to the rzv2h_icu_register_dma_req() function in the .register_dma_req field of the chip-specific structure to allow for other implementations. Do the same for the default request value, RZV2H_ICU_DMAC_REQ_NO_DEFAULT, and place it into .dma_req_no_default. While at it, factor out the logic that calls .register_dma_req() or rz_dmac_set_dmars_register() into a separate function to remove some code duplication. Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260105114445.878262-3-cosmin-gabriel.tanislav.xa@renesas.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-03-09dmaengine: sh: rz_dmac: make error interrupt optionalCosmin Tanislav-10/+9
The Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs do not have an error interrupt for the DMACs, and the current driver implementation does not make much use of it. To prepare for adding support for these SoCs, do not error out if the error interrupt is missing. Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260105114445.878262-2-cosmin-gabriel.tanislav.xa@renesas.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-03-09dmaengine: fsl-qdma: Use dev_err_probe() to simplify codeFrank Li-28/+19
Use dev_err_probe() to simplify code. No functional change. Signed-off-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/20260225-mxsdma-module-v3-13-8f798b13baa6@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-03-09dmaengine: fsl-edma: Use dev_err_probe() to simplify codeFrank Li-27/+20
Use dev_err_probe() to simplify code. No functional change. Signed-off-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/20260225-mxsdma-module-v3-12-8f798b13baa6@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-03-09dmaengine: fsl-edma: Use managed API dmaenginem_async_device_register()Frank Li-6/+2
Use managed API dmaenginem_async_device_register() and devm_of_dma_controller_register() to simple code. Signed-off-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/20260225-mxsdma-module-v3-11-8f798b13baa6@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-03-09dmaengine: imx-sdma: Use dev_err_probe() to simplify codeFrank Li-8/+5
Use dev_err_probe() to simplify code. No functional change. Signed-off-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/20260225-mxsdma-module-v3-10-8f798b13baa6@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-03-09dmaengine: imx-sdma: Use managed API to simplify codeFrank Li-14/+7
Use managed API devm_kzalloc(), dmaenginem_async_device_register() and devm_of_dma_controller_register() to simple code. No functional change. Signed-off-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/20260225-mxsdma-module-v3-9-8f798b13baa6@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-03-09dmaengine: imx-sdma: Use devm_clk_get_prepared() to simplify codeFrank Li-21/+5
Use devm_clk_get_prepared() to simplify code. No functional change. Signed-off-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/20260225-mxsdma-module-v3-8-8f798b13baa6@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-03-09dmaengine: mxs-dma: Turn MXS_DMA as tristateJindong Yue-1/+1
Use tristate for mxs-dma to support module building. Signed-off-by: Jindong Yue <jindong.yue@nxp.com> Signed-off-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/20260225-mxsdma-module-v3-7-8f798b13baa6@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-03-09dmaengine: mxs-dma: Add module license and descriptionJindong Yue-0/+3
Module license string is required for loading it as a module. Signed-off-by: Jindong Yue <jindong.yue@nxp.com> Signed-off-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/20260225-mxsdma-module-v3-6-8f798b13baa6@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-03-09dmaengine: mxs-dma: Use managed API devm_of_dma_controller_register()Frank Li-1/+1
Use managed API devm_of_dma_controller_register() to prepare support module remove. Signed-off-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/20260225-mxsdma-module-v3-5-8f798b13baa6@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-03-09dmaengine: mxs-dma: Use dev_err_probe() to simplify codeFrank Li-13/+7
Use dev_err_probe() simplify code. No functional change. Signed-off-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/20260225-mxsdma-module-v3-4-8f798b13baa6@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-03-09dmaengine: mxs-dma: Use local dev variable in probe()Frank Li-9/+10
Introduce a local dev variable in probe() to avoid repeated use of &pdev->dev throughout the function. No functional change. Signed-off-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/20260225-mxsdma-module-v3-3-8f798b13baa6@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-03-09dmaengine: mxs-dma: Fix missing return value from of_dma_controller_register()Frank Li-0/+1
Propagate the return value of of_dma_controller_register() in probe() instead of ignoring it. Fixes: a580b8c5429a6 ("dmaengine: mxs-dma: add dma support for i.MX23/28") Signed-off-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/20260225-mxsdma-module-v3-2-8f798b13baa6@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-03-09dmaengine: xilinx: Update kernel-doc commentsVinod Koul-0/+2
Two members of struct xdma_desc_block are not descibed leading to warnings, document them. Warning: drivers/dma/xilinx/xdma.c:75 struct member 'last_interrupt' not described in 'xdma_chan' Warning: drivers/dma/xilinx/xdma.c:75 struct member 'stop_requested' not described in 'xdma_chan' Link: https://patch.msgid.link/20260227022905.233721-1-vkoul@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-03-09dmaengine: xilinx: Simplify with scoped for each OF child loopKrzysztof Kozlowski-5/+3
Use scoped for-each loop when iterating over device nodes to make code a bit simpler. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260301142158.90319-2-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-03-09dmaengine: switchtec-dma: Implement descriptor submissionKelvin Cao-0/+225
On prep, a spin lock is taken and the next entry in the circular buffer is filled. On submit, the spin lock just needs to be released as the requests are already pending. When switchtec_dma_issue_pending() is called, the sq_tail register is written to indicate there are new jobs for the dma engine to start on. Pause and resume operations are implemented by writing to a control register. Signed-off-by: Kelvin Cao <kelvin.cao@microchip.com> Co-developed-by: George Ge <george.ge@microchip.com> Signed-off-by: George Ge <george.ge@microchip.com> Reviewed-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Logan Gunthorpe <logang@deltatee.com> Link: https://patch.msgid.link/20260302210419.3656-4-logang@deltatee.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-03-09dmaengine: switchtec-dma: Implement hardware initialization and cleanupKelvin Cao-2/+1005
Initialize the hardware and create the dma channel queues. Signed-off-by: Kelvin Cao <kelvin.cao@microchip.com> Co-developed-by: George Ge <george.ge@microchip.com> Signed-off-by: George Ge <george.ge@microchip.com> Reviewed-by: Christoph Hellwig <hch@lst.de> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Logan Gunthorpe <logang@deltatee.com> Link: https://patch.msgid.link/20260302210419.3656-3-logang@deltatee.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-03-09dmaengine: switchtec-dma: Introduce Switchtec DMA engine skeletonKelvin Cao-0/+219
Some Switchtec Switches can expose DMA engines via extra PCI functions on the upstream ports. At most one such function can be supported on each upstream port. Each function can have one or more DMA channels. This patch is just the core PCI driver skeleton and dma engine registration. Signed-off-by: Kelvin Cao <kelvin.cao@microchip.com> Co-developed-by: George Ge <george.ge@microchip.com> Signed-off-by: George Ge <george.ge@microchip.com> Reviewed-by: Christoph Hellwig <hch@lst.de> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Logan Gunthorpe <logang@deltatee.com> Link: https://patch.msgid.link/20260302210419.3656-2-logang@deltatee.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-03-09dmaengine: dma-axi-dmac: Gracefully terminate HW cyclic transfersNuno Sá-13/+91
Add support for gracefully terminating hardware cyclic DMA transfers when a new transfer is queued and is flagged with DMA_PREP_LOAD_EOT. Without this, cyclic transfers would continue indefinitely until we brute force it with .device_terminate_all(). When a new descriptor is queued while a cyclic transfer is active, mark the cyclic transfer for termination. For hardware with scatter-gather support, modify the last segment flags to trigger end-of-transfer. For non-SG hardware, clear the CYCLIC flag to allow natural completion. Older IP core versions (pre-4.6.a) can prefetch data when clearing the CYCLIC flag, causing corruption in the next transfer. Work around this by disabling and re-enabling the core to flush prefetched data. The cyclic_eot flag tracks transfers marked for termination, preventing new transfers from starting until the cyclic one completes. Non-EOT transfers submitted after cyclic transfers are discarded with a warning. Also note that for hardware cyclic transfers not using SG, we need to make sure that chan->next_desc is also set to NULL (so we can look at possible EOT transfers) and we also need to move the queue check to after axi_dmac_get_next_desc() because with hardware based cyclic transfers we might get the queue marked as full and hence we would not be able to check for cyclic termination. Signed-off-by: Nuno Sá <nuno.sa@analog.com> Link: https://patch.msgid.link/20260303-axi-dac-cyclic-support-v2-5-0db27b4be95a@analog.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-03-09dmaengine: dma-axi-dmac: Gracefully terminate SW cyclic transfersNuno Sá-1/+33
As of now, to terminate a cyclic transfer, one pretty much needs to use brute force and terminate all transfers with .device_terminate_all(). With this change, when a cyclic transfer terminates (and generates an EOT interrupt), look at any new pending transfer with the DMA_PREP_LOAD_EOT flag set. If there is one, the current cyclic transfer is terminated and the next one is enqueued. If the flag is not set, that transfer is ignored. Signed-off-by: Nuno Sá <nuno.sa@analog.com> Link: https://patch.msgid.link/20260303-axi-dac-cyclic-support-v2-4-0db27b4be95a@analog.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-03-09dmaengine: dma-axi-dmac: Add helper for getting next descNuno Sá-10/+23
Add a new helper for getting the next valid struct axi_dmac_desc. This will be extended in follow up patches to support to gracefully terminate cyclic transfers. Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Nuno Sá <nuno.sa@analog.com> Link: https://patch.msgid.link/20260303-axi-dac-cyclic-support-v2-3-0db27b4be95a@analog.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-03-09dmaengine: dma-axi-dmac: Add cyclic transfers in ↵Nuno Sá-1/+6
.device_prep_peripheral_dma_vec() Add support for cyclic transfers by checking the DMA_PREP_REPEAT flag. If the flag is set, close the loop and clear the flag for the last segment (the same done for .device_prep_dma_cyclic(). Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Nuno Sá <nuno.sa@analog.com> Link: https://patch.msgid.link/20260303-axi-dac-cyclic-support-v2-2-0db27b4be95a@analog.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-03-09dmaengine: ioatdma: make sysfs attributes constThomas Weißschuh-10/+10
The ioat_sysfs_entry structures are never modified, mark them as read-only. Signed-off-by: Thomas Weißschuh <linux@weissschuh.net> Acked-by: Dave Jiang <dave.jiang@intel.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/20260304-sysfs-const-ioat-v2-4-b9b82651219b@weissschuh.net Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-03-09dmaengine: ioatdma: make ioat_ktype constThomas Weißschuh-4/+4
ioat_ktype is never modified, so make it const. Signed-off-by: Thomas Weißschuh <linux@weissschuh.net> Acked-by: Dave Jiang <dave.jiang@intel.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/20260304-sysfs-const-ioat-v2-3-b9b82651219b@weissschuh.net Signed-off-by: Vinod Koul <vkoul@kernel.org>
2026-03-09dmaengine: ioatdma: move sysfs entry definition out of headerThomas Weißschuh-6/+6
Move struct ioat_sysfs_entry into sysfs.c because it is only used in it. Signed-off-by: Thomas Weißschuh <linux@weissschuh.net> Reviewed-by: Frank Li <Frank.Li@nxp.com> Acked-by: Dave Jiang <dave.jiang@intel.com> Link: https://patch.msgid.link/20260304-sysfs-const-ioat-v2-2-b9b82651219b@weissschuh.net Signed-off-by: Vinod Koul <vkoul@kernel.org>
generated by cgit v1.2.3 (git 2.46.0) at 2026-04-25 11:14:06 +0000