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path: root/drivers/gpu/drm/xe/regs
AgeCommit message (Expand)AuthorLines
2026-03-23drm/xe: Implement recent spec updates to Wa_16025250150Matt Roper-0/+1
2026-03-23drm/xe: Add PR_CTR_CTRL/THRSH register definitionsMichal Wajdeczko-0/+8
2026-03-17Merge tag 'drm-intel-next-2026-03-16' of https://gitlab.freedesktop.org/drm/i...Dave Airlie-2/+3
2026-03-10drm/xe: Translate C-state "reset value" into RC6Gustavo Sousa-0/+1
2026-03-10drm/xe/xe3p: Drop Wa_16028780921Gustavo Sousa-3/+0
2026-03-10drm/xe/nvlp: Implement Wa_14026539277Gustavo Sousa-0/+4
2026-03-10drm/xe: Allow per queue programming of COMMON_SLICE_CHICKEN3 bit13Lionel Landwerlin-0/+1
2026-03-10drm/xe: Add Wa_14026578760Varun Gupta-0/+3
2026-03-05drm/xe/xe_hw_error: Add support for PVC SoC errorsRiana Tauro-0/+25
2026-03-05drm/xe/xe_hw_error: Add support for Core-Compute errorsRiana Tauro-9/+52
2026-03-04drm/intel: add pick.h for the various "picker" helpersJani Nikula-2/+3
2026-02-27drm/xe/tuning: Apply windower hardware filtering setting on Xe3 and Xe3pMatt Roper-0/+1
2026-02-19drm/xe/xe3p_lpg: Add Wa_14026781792Nitin Gote-0/+1
2026-02-19drm/xe/wa: Steer RMW of MCR registers while building default LRCMatt Roper-0/+6
2026-02-10drm/xe/xe3p_lpg: Set STLB bank hash mode to 4KBAradhya Bhatia-0/+2
2026-02-10drm/xe/xe3p_lpg: Extend 'group ID' mask sizeMatt Roper-1/+1
2026-02-10drm/xe/xe3p_lpg: Add initial workarounds for graphics version 35.10Shekhar Chauhan-0/+16
2026-02-09drm/xe/guc: Add Wa_14025883347 for GuC DMA failure on resetSk Anirban-0/+8
2026-02-06drm/xe/xe3p_xpc: XeCore mask spans four registersMatt Roper-0/+2
2026-02-05drm/xe: Add GSC to powergate_infoVinay Belgaumkar-0/+1
2026-01-14drm/xe/mert: Improve handling of MERT CAT errorsMichal Wajdeczko-4/+6
2026-01-12drm/xe/hwmon: Expose individual VRAM channel temperatureKarthik Poosa-0/+3
2026-01-09drm/xe: Allow compressible surfaces to be 1-way coherentXin Wang-0/+6
2025-12-23drm/xe/soc_remapper: Add system controller config for SoC remapperUmesh Nerlige Ramappa-0/+1
2025-12-23drm/xe/soc_remapper: Use SoC remapper helper from VSEC codeUmesh Nerlige Ramappa-3/+13
2025-12-16drm/xe/oa/uapi: Expose MERT OA unitAshutosh Dixit-0/+9
2025-12-12drm/xe: Track pre-production workaround supportMatt Roper-0/+3
2025-12-12drm/xe: Create page reclaim list on unbindBrian Nguyen-0/+1
2025-12-04drm/xe/rtp: Whitelist OAM MMIO trigger registersAshutosh Dixit-0/+8
2025-12-01drm/xe/xe3_lpg: Apply Wa_16028005424Balasubramani Vivekanandan-0/+3
2025-11-25drm/xe/pf: Handle MERT catastrophic errorsLukasz Laguna-0/+5
2025-11-25drm/xe/pf: Add TLB invalidation support for MERTLukasz Laguna-0/+4
2025-11-25drm/xe/pf: Configure LMTT in MERTLukasz Laguna-0/+13
2025-11-10drm/xe: Use SG_TILE_ADDR_RANGE instead of TILE_ADDR_RANGEFei Yang-1/+2
2025-10-30drm/xe/cri: Add new performance limit reasons bitsSk Anirban-0/+13
2025-10-29drm/xe/xe_debugfs: Expose G7 package state residency counter through debugfsMohammed Thasleem-0/+1
2025-10-27drm/xe/xe3: Add WA_14024681466 for Xe3_LPGNitin Gote-0/+1
2025-10-20drm/xe/xe3p_lpm: Add special check in Media GT for Main GAMCTRLBalasubramani Vivekanandan-0/+6
2025-10-20drm/xe/xe3p_lpm: Configure MAIN_GAMCTRL_QUEUE_SELECTBrian Welty-0/+3
2025-10-18drm/xe/xe3p_xpc: Add support for compute walker for non-MSIxLucas De Marchi-0/+1
2025-10-18drm/xe/irq: Check fuse mask for media enginesLucas De Marchi-0/+3
2025-10-18drm/xe/irq: Rename bits used with all enginesLucas De Marchi-2/+2
2025-10-17drm/xe/xe3p: Dump CSMQDEBUG registerWang Xin-0/+2
2025-10-17drm/xe: Dump CURRENT_LRCA registerWang Xin-0/+2
2025-10-17drm/xe/xe3p: Determine service copy availability from fuseMatt Roper-0/+3
2025-10-17drm/xe: Drop CTC_MODE register readBalasubramani Vivekanandan-4/+0
2025-10-13drm/xe/i2c: Wire up reset/postinstall for I2C IRQRaag Jadav-0/+3
2025-10-10drm/xe: Enable media sampler power gatingVinay Belgaumkar-0/+1
2025-09-18drm/xe/lrc: Allow INDIRECT_CTX for more engine classesLucas De Marchi-3/+0
2025-09-05drm/xe/xe2hpg: Add Wa_18041344222 for Xe2_HPGHarish Chegondi-0/+1
generated by cgit v1.2.3 (git 2.46.0) at 2026-05-04 05:30:58 +0000