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2025-10-04Merge tag 'mtd/for-6.18' of ↵Linus Torvalds28-2286/+1935
git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux Pull MTD updates from Miquel Raynal: "MTD core: - Bad blocks increment is skipped if the block is already known bad (improves user statistics relevance) - Expose the OOB layout via debugfs Raw NAND: - Add support for Loongson-2K1000 and Loongson-2K0500 NAND controllers, including extra features, such as chip select and 6-byte NAND ID reading support - Drop the s3c2410 driver SPI NAND: - Important SPI NAND continuous read improvements and fixes - Add support for FudanMicro FM25S01A - Add support for continuous reads in Gigadevice vendor driver ECC: - Add support for the Realtek ECC engine SPI NOR: - Some flashes can't perform reads or writes with start or end being an odd number in Octal DTR mode. File systems like UBIFS can request such reads or writes, causing the transaction to error out. Pad the read or write transactions with extra bytes to avoid this problem. And the usual amount of various miscellaneous fixes" * tag 'mtd/for-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux: (46 commits) mtd: rawnand: sunxi: drop unused module alias mtd: rawnand: stm32_fmc2: drop unused module alias mtd: rawnand: rockchip: drop unused module alias mtd: rawnand: pl353: drop unused module alias mtd: rawnand: omap2: drop unused module alias mtd: rawnand: atmel: drop unused module alias mtd: onenand: omap2: drop unused module alias mtd: hyperbus: hbmc-am654: drop unused module alias mtd: jedec_probe: use struct_size() helper for cfiq allocation mtd: cfi: use struct_size() helper for cfiq allocation mtd: nand: raw: gpmi: fix clocks when CONFIG_PM=N mtd: rawnand: omap2: fix device leak on probe failure mtd: rawnand: atmel: Fix error handling path in atmel_nand_controller_add_nands mtd: nand: realtek-ecc: Add Realtek external ECC engine support dt-bindings: mtd: Add realtek,rtl9301-ecc mtd: spinand: repeat reading in regular mode if continuous reading fails mtd: spinand: try a regular dirmap if creating a dirmap for continuous reading fails mtd: spinand: fix direct mapping creation sizes mtd: rawnand: fsmc: Default to autodetect buswidth mtd: nand: move nand_check_erased_ecc_chunk() to nand/core ...
2025-10-03Merge tag 'nand/for-6.18' into mtd/nextMiquel Raynal22-2275/+1932
* Raw NAND: - Add support for Loongson-2K1000 and Loongson-2K0500 NAND controllers, including extra features, such as chip select and 6-byte NAND ID reading support. - Drop the s3c2410 driver. * SPI NAND: - Important SPI NAND continuous read improvements and fixes. - Add support for FudanMicro FM25S01A. - Add support for continuous reads in Gigadevice vendor driver. * ECC: - Add support for the Realtek ECC engine. This PR comes with the usual amount of various miscellaneous fixes. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2025-09-29mtd: rawnand: sunxi: drop unused module aliasJohan Hovold1-1/+0
The driver has never supported anything but OF probing so drop the unused platform module alias. Signed-off-by: Johan Hovold <johan@kernel.org> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2025-09-29mtd: rawnand: stm32_fmc2: drop unused module aliasJohan Hovold1-1/+0
The driver has never supported anything but OF probing so drop the unused platform module alias. Signed-off-by: Johan Hovold <johan@kernel.org> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2025-09-29mtd: rawnand: rockchip: drop unused module aliasJohan Hovold1-1/+0
The driver has never supported anything but OF probing so drop the unused platform module alias. Signed-off-by: Johan Hovold <johan@kernel.org> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2025-09-29mtd: rawnand: pl353: drop unused module aliasJohan Hovold1-1/+0
The driver has never supported anything but OF probing so drop the unused platform module alias. Signed-off-by: Johan Hovold <johan@kernel.org> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2025-09-29mtd: rawnand: omap2: drop unused module aliasJohan Hovold1-1/+0
The driver only supports OF probing since commit 086c321ec57b ("mtd: nand: omap2: Remove omap_nand_platform_data") so drop the unused platform module alias. Signed-off-by: Johan Hovold <johan@kernel.org> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2025-09-29mtd: rawnand: atmel: drop unused module aliasJohan Hovold1-1/+0
The driver only supports OF probing since commit f88fc122cc34 ("mtd: nand: Cleanup/rework the atmel_nand driver") so drop the unused platform module alias. Signed-off-by: Johan Hovold <johan@kernel.org> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2025-09-29mtd: onenand: omap2: drop unused module aliasJohan Hovold1-1/+0
The driver only supports OF probing since commit a758f50f10cf ("mtd: onenand: omap2: Configure driver from DT") so drop the unused platform module alias. Signed-off-by: Johan Hovold <johan@kernel.org> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2025-09-29mtd: nand: raw: gpmi: fix clocks when CONFIG_PM=NMaarten Zanders1-3/+11
Commit f04ced6d545e ("mtd: nand: raw: gpmi: improve power management handling") moved all clock handling into PM callbacks. With CONFIG_PM disabled, those callbacks are missing, leaving the driver unusable. Add clock init/teardown for !CONFIG_PM builds to restore basic operation. Keeping the driver working without requiring CONFIG_PM is preferred over adding a Kconfig dependency. Fixes: f04ced6d545e ("mtd: nand: raw: gpmi: improve power management handling") Signed-off-by: Maarten Zanders <maarten@zanders.be> Cc: stable@vger.kernel.org Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2025-09-29mtd: rawnand: omap2: fix device leak on probe failureJohan Hovold1-5/+21
Make sure to drop the reference to the elm device taken by of_find_device_by_node() during probe on errors and on driver unload. Fixes: 62116e5171e0 ("mtd: nand: omap2: Support for hardware BCH error correction.") Signed-off-by: Johan Hovold <johan@kernel.org> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2025-09-29mtd: rawnand: atmel: Fix error handling path in atmel_nand_controller_add_nandsErick Karanja1-2/+2
In case of a jump to the err label due to atmel_nand_create() or atmel_nand_controller_add_nand() failure, the reference to nand_np need to be released Use for_each_child_of_node_scoped() to fix the issue. Fixes: f88fc122cc34 ("mtd: nand: Cleanup/rework the atmel_nand driver") Signed-off-by: Erick Karanja <karanja99erick@gmail.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2025-09-29mtd: nand: realtek-ecc: Add Realtek external ECC engine supportMarkus Stockhausen3-0/+473
The Realtek RTl93xx switch SoC series has a built in ECC controller that can provide BCH6 or BCH12 over 512 data and 6 tag bytes. It generates 10 (BCH6) or 20 (BCH12) bytes of parity. This engine will most likely work in conjunction with the Realtek spi-mem based NAND controller but can work on its own. Therefore the initial implementation will be of type external. Remark! The engine can support any data blocks that are multiples of 512 bytes. For now limit it to data+oob layouts that have been analyzed from existing devices. This way it keeps compatibility and pre-existing vendor data can be read. Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2025-09-29mtd: spinand: repeat reading in regular mode if continuous reading failsMikhail Kshevetskiy1-4/+21
Continuous reading may result in multiple flash pages reading in one operation. Unfortunately, not all spinand controllers support such large reading. They will read less data. Unfortunately, the operation can't be continued. In this case: * disable continuous reading on this (not good enough) spi controller * repeat reading in regular mode. Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2025-09-29mtd: spinand: try a regular dirmap if creating a dirmap for continuous ↵Mikhail Kshevetskiy1-8/+35
reading fails Continuous reading may result in multiple flash pages reading in one operation. Typically only one flash page has read/written (a little bit more than 2-4 Kb), but continuous reading requires the spi controller to read up to 512 Kb in one operation without toggling CS in beetween. Roughly speaking spi controllers can be divided on 2 categories: * spi controllers without dirmap acceleration support * spi controllers with dirmap acceleration support Firt of them will have issues with continuous reading if restriction on the transfer length is implemented in the adjust_op_size() handler. Second group often supports acceleration of single page only reading. Thus enabling of continuous reading can break flash reading. This patch tries to create dirmap for continuous reading first and fallback to regular reading if spi controller refuses to create it. Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2025-09-29mtd: spinand: fix direct mapping creation sizesMikhail Kshevetskiy1-7/+7
Continuous mode is only supported for data reads, thus writing requires only single flash page mapping. Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2025-09-18mtd: rawnand: fsmc: Default to autodetect buswidthLinus Walleij1-1/+5
If you don't specify buswidth 2 (16 bits) in the device tree, FSMC doesn't even probe anymore: fsmc-nand 10100000.flash: FSMC device partno 090, manufacturer 80, revision 00, config 00 nand: device found, Manufacturer ID: 0x20, Chip ID: 0xb1 nand: ST Micro 10100000.flash nand: bus width 8 instead of 16 bits nand: No NAND device found fsmc-nand 10100000.flash: probe with driver fsmc-nand failed with error -22 With this patch to use autodetection unless buswidth is specified, the device is properly detected again: fsmc-nand 10100000.flash: FSMC device partno 090, manufacturer 80, revision 00, config 00 nand: device found, Manufacturer ID: 0x20, Chip ID: 0xb1 nand: ST Micro NAND 128MiB 1,8V 16-bit nand: 128 MiB, SLC, erase size: 128 KiB, page size: 2048, OOB size: 64 fsmc-nand 10100000.flash: Using 1-bit HW ECC scheme Scanning device for bad blocks I don't know where or how this happened, I think some change in the nand core. Cc: stable@vger.kernel.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2025-09-18mtd: nand: move nand_check_erased_ecc_chunk() to nand/coreMarkus Stockhausen2-131/+131
The check function for bitflips in erased blocks will be needed by the Realtek ECC engine driver (which is currently under development). Right now it is located in raw/nand_base.c. While this is sufficient for the current usecases, there is no real dependency for an ECC engine on the raw nand library. Move the function over to a more generic place in core library. Suggested-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2025-09-18mtd: nand: ecc-mxic: Lower log level during initMiquel Raynal1-7/+7
A working init shall be silent rather than exposing the configuration with kernel messages at the error level. Thwart myself from the past and use the debug level for these. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2025-09-11mtd: use vmalloc_array and vcalloc to simplify codeQianfeng Rong1-4/+3
Remove array_size() calls and replace vmalloc(array_size()) with vmalloc_array() and vzalloc(array_size()) with vcalloc() to simplify the code. Compile-tested only. Signed-off-by: Qianfeng Rong <rongqianfeng@vivo.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2025-09-10mtd: rawnand: loongson: Add Loongson-2K1000 NAND controller supportBinbin Zhou1-0/+49
The Loongson-2K1000 NAND controller is also similar to the Loongson-1C. It supports a maximum capacity of 16GB FLASH per chip with a maximum page size of 8KB, and it supports up to 4 chip selects and 4 RDY signals. The key difference from the Loongson-2K0500 is that it requires explicit configuration of the DMA control route. Typically, it is configured as APBDMA0. Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2025-09-10mtd: rawnand: loongson: Add Loongson-2K0500 NAND controller supportBinbin Zhou2-2/+53
The Loongson-2K0500 NAND controller is similar to the Loongson-1C. It supports a maximum capacity of 16GB FLASH per chip with a maximum page size of 8KB, and it supports up to 4 chip selects and 4 RDY signals. Its DMA controller is defaulted to APBDMA0. Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2025-09-10mtd: rawnand: loongson: Add nand chip select supportBinbin Zhou1-26/+90
The page address register describes the page address of the starting address for NAND read/write/erase operations. According to the manual, it consists of two parts: {chip select, page number} The `chip select` is fixed at 2 bits, and the `page number` is determined based on the actual capacity of the single-chip memory. Therefore we need to determine the `chip select` bits base on the `page number`. For example, for a 1GB capacity chip (2K page size), it has 1M pages. Thus, [19:0] is used to represent the page number, and [21:20] represents the chip select. Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2025-09-10mtd: rawnand: loongson: Add 6-byte NAND ID reading supportKeguang Zhang1-6/+23
Loongson-1C and Loongson-2K SoCs support NAND flash chips with 6-byte ID. However, the current implementation only handles 5-byte ID which can lead to incorrect chip detection. Extend loongson_nand_read_id_type_exec() to support 6-byte NAND ID. Signed-off-by: Keguang Zhang <keguang.zhang@gmail.com> Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2025-09-10mtd: rawnand: loongson1: Rename the prefix from ls1x to loongsonBinbin Zhou3-169/+176
I am going to introduce the NAND controllers of the Loongson-2K series CPUs, which are similar to Loongson-1. As preparation, rename all prefixes from Loongson1-specific to Loongson-generic. No functional change intended. Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2025-09-10mtd: rawnand: atmel: Fix pulse read timing for certain flash chipsAlexander Dahl1-4/+9
Prevent PMECC errors when reading from AMD/Spansion S34ML02G1 flash on SAM9X60 SoC, after switching to ONFI timing mode 3. From reading the S34ML02G1 and the SAM9X60 datasheets again, it seems like we have to wait tREA after rising RE# before sampling the data. Thus pulse must be at least tREA. The previous approach to set this timing worked on sam9g20 and sama5d2 with the same flash (S34ML02G1), probably because those have a slower mck clock rate and thus the resolution of the timings setup is not as tight as with sam9x60. The approach to fix the issue was carried over from u-boot, which itself got it from at91bootstrap. It has been successfully tested in at91bootstrap, U-Boot and Linux on sam9x60 and sama5d2, for several months here. Link: https://github.com/linux4sam/at91bootstrap/issues/174 Link: https://github.com/linux4sam/at91bootstrap/commit/e2dfd8141d00613a37acee66ef5724f70f34a538 Link: https://lore.kernel.org/u-boot/20240415075755.780653-1-ada@thorsis.com/ Link: https://source.denx.de/u-boot/u-boot/-/commit/344e2f2cd4a407f847b301804f37d036e8a0a10c Cc: Li Bin <bin.li@microchip.com> Signed-off-by: Alexander Dahl <ada@thorsis.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2025-09-10mtd: nand: ecc: fix "writen"->"written"Xichao Zhao1-1/+1
Trivial fix to spelling mistake in comment text. Signed-off-by: Xichao Zhao <zhao.xichao@vivo.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2025-09-05mtd: spinand: winbond: Fix oob_layout for W25N01JWSanthosh Kumar K1-1/+36
Fix the W25N01JW's oob_layout according to the datasheet [1] [1] https://www.winbond.com/hq/product/code-storage-flash-memory/qspinand-flash/?__locale=en&partNo=W25N01JW Fixes: 6a804fb72de5 ("mtd: spinand: winbond: add support for serial NAND flash") Cc: Sridharan S N <quic_sridsn@quicinc.com> Cc: stable@vger.kernel.org Signed-off-by: Santhosh Kumar K <s-k6@ti.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2025-09-02mtd: rawnand: s3c2410: Drop driver (no actual S3C64xx user)Krzysztof Kozlowski3-1219/+0
The s3c2410 NAND driver still supports S3C64xx platform, which in general is supported in the kernel. There are however no references of "s3c6400-nand" platform device ID or "s3c24xx-nand" driver, thus this driver cannot be instantiated for S3C64xx platform and is basically unused. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2025-09-01mtd: rawnand: s3c2410: Drop S3C2410 supportKrzysztof Kozlowski1-38/+0
Samsung S3C24xx family of SoCs was removed from the Linux kernel in the commit 61b7f8920b17 ("ARM: s3c: remove all s3c24xx support"), in January 2023. There are no in-kernel users of its compatibles and platform IDs. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2025-09-01mtd: rawnand: pl353: Use int type to store negative error codesQianfeng Rong1-1/+1
Change the 'ret' variable from u32 to int in pl35x_nand_probe() to store negative error codes or zero; Storing the negative error codes in unsigned type, doesn't cause an issue at runtime but can be confusing. Additionally, assigning negative error codes to unsigned type may trigger a GCC warning when the -Wsign-conversion flag is enabled. No effect on runtime. Signed-off-by: Qianfeng Rong <rongqianfeng@vivo.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2025-08-28mtd: nand: raw: atmel: Respect tAR, tCLR in read setup timingAlexander Sverdlin1-3/+13
Having setup time 0 violates tAR, tCLR of some chips, for instance TOSHIBA TC58NVG2S3ETAI0 cannot be detected successfully (first ID byte being read duplicated, i.e. 98 98 dc 90 15 76 14 03 instead of 98 dc 90 15 76 ...). Atmel Application Notes postulated 1 cycle NRD_SETUP without explanation [1], but it looks more appropriate to just calculate setup time properly. [1] Link: https://ww1.microchip.com/downloads/aemDocuments/documents/MPU32/ApplicationNotes/ApplicationNotes/doc6255.pdf Cc: stable@vger.kernel.org Fixes: f9ce2eddf176 ("mtd: nand: atmel: Add ->setup_data_interface() hooks") Signed-off-by: Alexander Sverdlin <alexander.sverdlin@siemens.com> Tested-by: Alexander Dahl <ada@thorsis.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2025-08-28mtd: spinand: add support for FudanMicro FM25S01ATianling Shen3-1/+76
Add support for FudanMicro FM25S01A SPI NAND. Datasheet: http://eng.fmsh.com/nvm/FM25S01A_ds_eng.pdf Signed-off-by: Tianling Shen <cnsztl@gmail.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2025-08-28mtd: spinand: gigadevice: Add continuous read supportTeng Wu1-2/+105
GD5F1GM9 supports a high-speed Continuous Read (CR) mode which allows the entire memory array to be read out by a single read command without re-issuing the 13h “Page Read to Cache” command for every page. Datasheet summary Feature register B0[3] (NR bit) 1 = Normal Read (default) 0 = Continuous Read (CR) ECC status register 7Ch Normal read: bits [3:0] → ECC status of last page Continuous read: bits [7:4] → accumulated max bit-flips over the whole sequential read operation. Datasheet: https://github.com/WT-886/DATASHEET/blob/main/GD5F1GM9-v1.0.pdf Signed-off-by: Teng Wu <gigadevice2025@gmail.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2025-08-28mtd: rawnand: stm32_fmc2: fix ECC overwriteChristophe Kerello1-3/+15
In case OOB write is requested during a data write, ECC is currently lost. Avoid this issue by only writing in the free spare area. This issue has been seen with a YAFFS2 file system. Signed-off-by: Christophe Kerello <christophe.kerello@foss.st.com> Cc: stable@vger.kernel.org Fixes: 2cd457f328c1 ("mtd: rawnand: stm32_fmc2: add STM32 FMC2 NAND flash controller driver") Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2025-08-28mtd: rawnand: stm32_fmc2: avoid overlapping mappings on ECC bufferChristophe Kerello1-19/+9
Avoid below overlapping mappings by using a contiguous non-cacheable buffer. [ 4.077708] DMA-API: stm32_fmc2_nfc 48810000.nand-controller: cacheline tracking EEXIST, overlapping mappings aren't supported [ 4.089103] WARNING: CPU: 1 PID: 44 at kernel/dma/debug.c:568 add_dma_entry+0x23c/0x300 [ 4.097071] Modules linked in: [ 4.100101] CPU: 1 PID: 44 Comm: kworker/u4:2 Not tainted 6.1.82 #1 [ 4.106346] Hardware name: STMicroelectronics STM32MP257F VALID1 SNOR / MB1704 (LPDDR4 Power discrete) + MB1703 + MB1708 (SNOR MB1730) (DT) [ 4.118824] Workqueue: events_unbound deferred_probe_work_func [ 4.124674] pstate: 60000005 (nZCv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--) [ 4.131624] pc : add_dma_entry+0x23c/0x300 [ 4.135658] lr : add_dma_entry+0x23c/0x300 [ 4.139792] sp : ffff800009dbb490 [ 4.143016] x29: ffff800009dbb4a0 x28: 0000000004008022 x27: ffff8000098a6000 [ 4.150174] x26: 0000000000000000 x25: ffff8000099e7000 x24: ffff8000099e7de8 [ 4.157231] x23: 00000000ffffffff x22: 0000000000000000 x21: ffff8000098a6a20 [ 4.164388] x20: ffff000080964180 x19: ffff800009819ba0 x18: 0000000000000006 [ 4.171545] x17: 6361727420656e69 x16: 6c6568636163203a x15: 72656c6c6f72746e [ 4.178602] x14: 6f632d646e616e2e x13: ffff800009832f58 x12: 00000000000004ec [ 4.185759] x11: 00000000000001a4 x10: ffff80000988af58 x9 : ffff800009832f58 [ 4.192916] x8 : 00000000ffffefff x7 : ffff80000988af58 x6 : 80000000fffff000 [ 4.199972] x5 : 000000000000bff4 x4 : 0000000000000000 x3 : 0000000000000000 [ 4.207128] x2 : 0000000000000000 x1 : 0000000000000000 x0 : ffff0000812d2c40 [ 4.214185] Call trace: [ 4.216605] add_dma_entry+0x23c/0x300 [ 4.220338] debug_dma_map_sg+0x198/0x350 [ 4.224373] __dma_map_sg_attrs+0xa0/0x110 [ 4.228411] dma_map_sg_attrs+0x10/0x2c [ 4.232247] stm32_fmc2_nfc_xfer.isra.0+0x1c8/0x3fc [ 4.237088] stm32_fmc2_nfc_seq_read_page+0xc8/0x174 [ 4.242127] nand_read_oob+0x1d4/0x8e0 [ 4.245861] mtd_read_oob_std+0x58/0x84 [ 4.249596] mtd_read_oob+0x90/0x150 [ 4.253231] mtd_read+0x68/0xac Signed-off-by: Christophe Kerello <christophe.kerello@foss.st.com> Cc: stable@vger.kernel.org Fixes: 2cd457f328c1 ("mtd: rawnand: stm32_fmc2: add STM32 FMC2 NAND flash controller driver") Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2025-08-28mtd: nand: qpic_common: use {cmd,data}_sgl_nitems for sg_init_table()Gabor Juhos1-4/+2
Since commit ddaad4ad774d ("mtd: nand: qpic_common: prevent out of bounds access of BAM arrays"), the {cmd,data}_sgl_nitems members in the 'bam_transaction' structure are containing the number of elements in the cmd/data scatter-gather lists. Change the qcom_clear_bam_transaction() function to use these numbers while reinitializing the sg lists instead of recomputing the number of elements to make it less error prone. Signed-off-by: Gabor Juhos <j4g8y7@gmail.com> Acked-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2025-08-28mtd: rawnand: nuvoton: Fix an error handling path in ma35_nand_chips_init()Christophe JAILLET1-2/+2
If a ma35_nand_chip_init() call fails, then a reference to 'nand_np' still needs to be released. Use for_each_child_of_node_scoped() to fix the issue. Fixes: 5abb5d414d55 ("mtd: rawnand: nuvoton: add new driver for the Nuvoton MA35 SoC") Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2025-07-31Merge tag 'mtd/for-6.17' of ↵Linus Torvalds20-121/+340
git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux Pull mtd updates from Miquel Raynal: "MTD changes: - Apart from a binding conversion to yaml, only minor changes/small fixes have been merged. Raw NAND changes: - Minor fixes for various controller drivers like DMA mapping checks, better timing derivations or bitflip statistics. - some Hynix NAND flashes were not supporting read-retries, so don't even try to do it SPI NAND changes: - In order to support high-speed modes, certain chips need extra configuration like adding more dummy cycles. This is now possible, especially on Winbond chips. - Aside from that, Gigadevice gets support for a new chip (GD5F1GM9). SPI NOR changes: - A notable changes is the fix for exiting 4-byte addressing on Infineon SEMPER flashes. These flashes do not support the standard EX4B opcode (E9h), and use a vendor-specific opcode (B8h) instead. - There is also a fix for unlocking flashes that are write-protected at power-on. This was caused by using an uninitialized mtd_info in spi_nor_try_unlock_all()" * tag 'mtd/for-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux: (26 commits) mtd: spinand: winbond: Add comment about the maximum frequency mtd: spinand: winbond: Enable high-speed modes on w35n0xjw mtd: spinand: winbond: Enable high-speed modes on w25n0xjw mtd: spinand: Add a ->configure_chip() hook mtd: spinand: Add a frequency field to all READ_FROM_CACHE variants mtd: spinand: Fix macro alignment spi: spi-mem: Take into account the actual maximum frequency spi: spi-mem: Use picoseconds for calculating the op durations mtd: rawnand: atmel: set pmecc data setup time mtd: spinand: propagate spinand_wait() errors from spinand_write_page() mtd: rawnand: fsmc: Add missing check after DMA map mtd: rawnand: rockchip: Add missing check after DMA map mtd: rawnand: hynix: don't try read-retry on SLC NANDs mtd: rawnand: atmel: Fix dma_mapping_error() address mtd: nand: brcmnand: fix mtd corrected bits stat mtd: rawnand: renesas: Add missing check after DMA map mtd: spinand: gigadevice: Add support for GD5F1GM9 chips mtd: nand: brcmnand: replace manual string choices with standard helpers mtd: map: Don't use "proxy" headers mtd: spi-nor: Fix spi_nor_try_unlock_all() ...
2025-07-30mtd: spinand: winbond: Add comment about the maximum frequencyMiquel Raynal1-0/+1
Clarify that Winbond octal capable chips may be clocked at up to 166MHz, which is their absolute maximum. No per-operation maximum value (captured with a "0" in the table) involves that in these cases the maximum frequency of the chip applies, ie. the one commonly described in the DT. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2025-07-30mtd: spinand: winbond: Enable high-speed modes on w35n0xjwMiquel Raynal2-4/+93
w35n0xjw chips can run at up to 166MHz in octal mode, but this is only possible after programming various VCR registers. Implement the new ->configure_chip() hook for this purpose. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2025-07-30mtd: spinand: winbond: Enable high-speed modes on w25n0xjwMiquel Raynal2-3/+44
w25n0xjw chips have a high-speed capability hidden in a configuration register. Once enabled, dual/quad SDR reads may be performed at a much higher frequency. Implement the new ->configure_chip() hook for this purpose and configure the SR4 register accordingly. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2025-07-30mtd: spinand: Add a ->configure_chip() hookMiquel Raynal1-2/+14
There is already a manufacturer hook, which is manufacturer specific but not chip specific. We no longer have access to the actual NAND identity at this stage so let's add a per-chip configuration hook to align the chip configuration (if any) with the core's setting. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2025-07-30mtd: spinand: Add a frequency field to all READ_FROM_CACHE variantsMiquel Raynal12-88/+88
These macros had initially no frequency field. When I added the "maximum operation frequency" field, I did it initially on very common macros and I decided to add an optional field for that (with VA_ARGS) in order to prevent massively unreadable changes. I then added new variants in the spinand.h header, and requested a frequency field for them by default. Some times later, I also added maximum frequencies to other existing variants, but I did it incorrectly, without noticing I was wrong because the field was optional. This mix is error prone, so let's do what I should have done since the very beginning: add a frequency field to all READ_FROM_CACHE variants. There is no functional change. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2025-07-30spi: spi-mem: Take into account the actual maximum frequencyMiquel Raynal1-1/+1
In order to pick the best variant, the duration of each typical operation is derived and then compared. These durations are based on the maximum capabilities of the chips, which are commonly the limiting factors. However there are other possible limiting pieces, such as the hardware layout, EMC considerations and in some cases, the SPI controller itself. We need to take this into account to further refine our variant choice, so let's use the actual frequency that will be used for the operation instead of the theoretical maximum. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Mark Brown <broonie@kernel.org>
2025-07-30mtd: rawnand: atmel: set pmecc data setup timeBalamanikandan Gunasundar1-0/+6
Setup the pmecc data setup time as 3 clock cycles for 133MHz as recommended by the datasheet. Fixes: f88fc122cc34 ("mtd: nand: Cleanup/rework the atmel_nand driver") Reported-by: Zixun LI <admin@hifiphile.com> Closes: https://lore.kernel.org/all/c015bb20-6a57-4f63-8102-34b3d83e0f5b@microchip.com Suggested-by: Ada Couprie Diaz <ada.coupriediaz@arm.com> Signed-off-by: Balamanikandan Gunasundar <balamanikandan.gunasundar@microchip.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2025-07-30mtd: spinand: propagate spinand_wait() errors from spinand_write_page()Gabor Juhos1-1/+4
Since commit 3d1f08b032dc ("mtd: spinand: Use the external ECC engine logic") the spinand_write_page() function ignores the errors returned by spinand_wait(). Change the code to propagate those up to the stack as it was done before the offending change. Cc: stable@vger.kernel.org Fixes: 3d1f08b032dc ("mtd: spinand: Use the external ECC engine logic") Signed-off-by: Gabor Juhos <j4g8y7@gmail.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2025-07-30mtd: rawnand: fsmc: Add missing check after DMA mapThomas Fourier1-0/+2
The DMA map functions can fail and should be tested for errors. Fixes: 4774fb0a48aa ("mtd: nand/fsmc: Add DMA support") Cc: stable@vger.kernel.org Signed-off-by: Thomas Fourier <fourier.thomas@gmail.com> Rule: add Link: https://lore.kernel.org/stable/20250702065806.20983-2-fourier.thomas%40gmail.com Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2025-07-30mtd: rawnand: rockchip: Add missing check after DMA mapThomas Fourier1-0/+15
The DMA map functions can fail and should be tested for errors. Fixes: 058e0e847d54 ("mtd: rawnand: rockchip: NFC driver for RK3308, RK2928 and others") Signed-off-by: Thomas Fourier <fourier.thomas@gmail.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2025-07-30mtd: rawnand: hynix: don't try read-retry on SLC NANDsHector Palacios1-2/+2
Some SLC NANDs like H27U4G8F2D expose a valid JEDEC ID yet they don't support the read-retry mechanism, and fail. Since SLC NANDs don't require read-retry, continue only if the bits per cell is bigger than 1. Signed-off-by: Hector Palacios <hector.palacios@digi.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
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