1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
|
// SPDX-License-Identifier: MIT
/*
* Copyright 2025 Advanced Micro Devices, Inc.
*
* Authors: AMD
*/
#include "dml2_internal_types.h"
#include "dml2_wrapper_fpu.h"
bool dml2_validate(const struct dc *in_dc, struct dc_state *context, struct dml2_context *dml2,
enum dc_validate_mode validate_mode)
{
bool out = false;
if (!dml2)
return false;
dml2_apply_debug_options(in_dc, dml2);
/* DML2.1 validation path */
if (dml2->architecture == dml2_architecture_21) {
out = dml21_validate(in_dc, context, dml2, validate_mode);
return out;
}
DC_FP_START();
/* Use dml_validate_only for DC_VALIDATE_MODE_ONLY and DC_VALIDATE_MODE_AND_STATE_INDEX path */
if (validate_mode != DC_VALIDATE_MODE_AND_PROGRAMMING)
out = dml2_validate_only(context, validate_mode);
else
out = dml2_validate_and_build_resource(in_dc, context, validate_mode);
DC_FP_END();
return out;
}
static void dml2_init(const struct dc *in_dc, const struct dml2_configuration_options *config, struct dml2_context **dml2)
{
if ((in_dc->debug.using_dml21) && (in_dc->ctx->dce_version >= DCN_VERSION_4_01)) {
dml21_reinit(in_dc, *dml2, config);
return;
}
// Store config options
(*dml2)->config = *config;
switch (in_dc->ctx->dce_version) {
case DCN_VERSION_3_5:
(*dml2)->v20.dml_core_ctx.project = dml_project_dcn35;
break;
case DCN_VERSION_3_51:
(*dml2)->v20.dml_core_ctx.project = dml_project_dcn351;
break;
case DCN_VERSION_3_6:
(*dml2)->v20.dml_core_ctx.project = dml_project_dcn36;
break;
case DCN_VERSION_3_2:
(*dml2)->v20.dml_core_ctx.project = dml_project_dcn32;
break;
case DCN_VERSION_3_21:
(*dml2)->v20.dml_core_ctx.project = dml_project_dcn321;
break;
case DCN_VERSION_4_01:
(*dml2)->v20.dml_core_ctx.project = dml_project_dcn401;
break;
default:
(*dml2)->v20.dml_core_ctx.project = dml_project_default;
break;
}
DC_FP_START();
initialize_dml2_ip_params(*dml2, in_dc, &(*dml2)->v20.dml_core_ctx.ip);
initialize_dml2_soc_bbox(*dml2, in_dc, &(*dml2)->v20.dml_core_ctx.soc);
initialize_dml2_soc_states(*dml2, in_dc, &(*dml2)->v20.dml_core_ctx.soc, &(*dml2)->v20.dml_core_ctx.states);
DC_FP_END();
}
bool dml2_create(const struct dc *in_dc, const struct dml2_configuration_options *config, struct dml2_context **dml2)
{
// TODO : Temporarily add DCN_VERSION_3_2 for N-1 validation. Remove DCN_VERSION_3_2 after N-1 validation phase is complete.
if ((in_dc->debug.using_dml21) && (in_dc->ctx->dce_version >= DCN_VERSION_4_01))
return dml21_create(in_dc, dml2, config);
// Allocate Mode Lib Ctx
*dml2 = dml2_allocate_memory();
if (!(*dml2))
return false;
dml2_init(in_dc, config, dml2);
return true;
}
void dml2_reinit(const struct dc *in_dc,
const struct dml2_configuration_options *config,
struct dml2_context **dml2)
{
if ((in_dc->debug.using_dml21) && (in_dc->ctx->dce_version >= DCN_VERSION_4_01)) {
dml21_reinit(in_dc, *dml2, config);
return;
}
dml2_init(in_dc, config, dml2);
}
|
