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path: root/drivers/usb/cdns3/cdns3-debug.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Cadence USBSS DRD Driver.
 * Debug header file.
 *
 * Copyright (C) 2018-2019 Cadence.
 *
 * Author: Pawel Laszczak <pawell@cadence.com>
 */
#ifndef __LINUX_CDNS3_DEBUG
#define __LINUX_CDNS3_DEBUG

#include "core.h"

static inline char *cdns3_decode_usb_irq(char *str,
					 enum usb_device_speed speed,
					 u32 usb_ists)
{
	int ret;

	ret = sprintf(str, "IRQ %08x = ", usb_ists);

	if (usb_ists & (USB_ISTS_CON2I | USB_ISTS_CONI)) {
		ret += sprintf(str + ret, "Connection %s\n",
			       usb_speed_string(speed));
	}
	if (usb_ists & USB_ISTS_DIS2I || usb_ists & USB_ISTS_DISI)
		ret += sprintf(str + ret, "Disconnection ");
	if (usb_ists & USB_ISTS_L2ENTI)
		ret += sprintf(str + ret, "suspended ");
	if (usb_ists & USB_ISTS_L1ENTI)
		ret += sprintf(str + ret, "L1 enter ");
	if (usb_ists & USB_ISTS_L1EXTI)
		ret += sprintf(str + ret, "L1 exit ");
	if (usb_ists & USB_ISTS_L2ENTI)
		ret += sprintf(str + ret, "L2 enter ");
	if (usb_ists & USB_ISTS_L2EXTI)
		ret += sprintf(str + ret, "L2 exit ");
	if (usb_ists & USB_ISTS_U3EXTI)
		ret += sprintf(str + ret, "U3 exit ");
	if (usb_ists & USB_ISTS_UWRESI)
		ret += sprintf(str + ret, "Warm Reset ");
	if (usb_ists & USB_ISTS_UHRESI)
		ret += sprintf(str + ret, "Hot Reset ");
	if (usb_ists & USB_ISTS_U2RESI)
		ret += sprintf(str + ret, "Reset");

	return str;
}

static inline  char *cdns3_decode_ep_irq(char *str,
					 u32 ep_sts,
					 const char *ep_name)
{
	int ret;

	ret = sprintf(str, "IRQ for %s: %08x ", ep_name, ep_sts);

	if (ep_sts & EP_STS_SETUP)
		ret += sprintf(str + ret, "SETUP ");
	if (ep_sts & EP_STS_IOC)
		ret += sprintf(str + ret, "IOC ");
	if (ep_sts & EP_STS_ISP)
		ret += sprintf(str + ret, "ISP ");
	if (ep_sts & EP_STS_DESCMIS)
		ret += sprintf(str + ret, "DESCMIS ");
	if (ep_sts & EP_STS_STREAMR)
		ret += sprintf(str + ret, "STREAMR ");
	if (ep_sts & EP_STS_MD_EXIT)
		ret += sprintf(str + ret, "MD_EXIT ");
	if (ep_sts & EP_STS_TRBERR)
		ret += sprintf(str + ret, "TRBERR ");
	if (ep_sts & EP_STS_NRDY)
		ret += sprintf(str + ret, "NRDY ");
	if (ep_sts & EP_STS_PRIME)
		ret += sprintf(str + ret, "PRIME ");
	if (ep_sts & EP_STS_SIDERR)
		ret += sprintf(str + ret, "SIDERRT ");
	if (ep_sts & EP_STS_OUTSMM)
		ret += sprintf(str + ret, "OUTSMM ");
	if (ep_sts & EP_STS_ISOERR)
		ret += sprintf(str + ret, "ISOERR ");
	if (ep_sts & EP_STS_IOT)
		ret += sprintf(str + ret, "IOT ");

	return str;
}

static inline char *cdns3_decode_epx_irq(char *str,
					 char *ep_name,
					 u32 ep_sts)
{
	return cdns3_decode_ep_irq(str, ep_sts, ep_name);
}

static inline char *cdns3_decode_ep0_irq(char *str,
					 int dir,
					 u32 ep_sts)
{
	return cdns3_decode_ep_irq(str, ep_sts,
				   dir ? "ep0IN" : "ep0OUT");
}

/**
 * Debug a transfer ring.
 *
 * Prints out all TRBs in the endpoint ring, even those after the Link TRB.
 *.
 */
static inline char *cdns3_dbg_ring(struct cdns3_endpoint *priv_ep,
				   struct cdns3_trb *ring, char *str)
{
	dma_addr_t addr = priv_ep->trb_pool_dma;
	struct cdns3_trb *trb;
	int trb_per_sector;
	int ret = 0;
	int i;

	trb_per_sector = GET_TRBS_PER_SEGMENT(priv_ep->type);

	trb = &priv_ep->trb_pool[priv_ep->dequeue];
	ret += sprintf(str + ret, "\n\t\tRing contents for %s:", priv_ep->name);

	ret += sprintf(str + ret,
		       "\n\t\tRing deq index: %d, trb: %p (virt), 0x%llx (dma)\n",
		       priv_ep->dequeue, trb,
		       (unsigned long long)cdns3_trb_virt_to_dma(priv_ep, trb));

	trb = &priv_ep->trb_pool[priv_ep->enqueue];
	ret += sprintf(str + ret,
		       "\t\tRing enq index: %d, trb: %p (virt), 0x%llx (dma)\n",
		       priv_ep->enqueue, trb,
		       (unsigned long long)cdns3_trb_virt_to_dma(priv_ep, trb));

	ret += sprintf(str + ret,
		       "\t\tfree trbs: %d, CCS=%d, PCS=%d\n",
		       priv_ep->free_trbs, priv_ep->ccs, priv_ep->pcs);

	if (trb_per_sector > TRBS_PER_SEGMENT)
		trb_per_sector = TRBS_PER_SEGMENT;

	if (trb_per_sector > TRBS_PER_SEGMENT) {
		sprintf(str + ret, "\t\tTransfer ring %d too big\n",
			trb_per_sector);
		return str;
	}

	for (i = 0; i < trb_per_sector; ++i) {
		trb = &ring[i];
		ret += sprintf(str + ret,
			"\t\t@%pad %08x %08x %08x\n", &addr,
			le32_to_cpu(trb->buffer),
			le32_to_cpu(trb->length),
			le32_to_cpu(trb->control));
		addr += sizeof(*trb);
	}

	return str;
}

#endif /*__LINUX_CDNS3_DEBUG*/
25-10-01 10:29:00 +0100'>2025-10-01mfd: 88pm886: Add GPADC cellDuje Mihanović1-0/+1 Add a cell for the PMIC's onboard General Purpose ADC. Acked-by: Karel Balej <balejk@matfyz.cz> # for the PMIC Signed-off-by: Duje Mihanović <duje@dujemihanovic.xyz> Link: https://lore.kernel.org/r/20250911-88pm886-gpadc-v4-3-60452710d3a0@dujemihanovic.xyz Signed-off-by: Lee Jones <lee@kernel.org> 2025-10-01mfd: vexpress-sysreg: Use more common syntax for compound literalsBartosz Golaszewski1-1/+1 The (typeof(foo)) construct is unusual in the kernel, use a more typical syntax by explicitly spelling out the type. Link: https://lore.kernel.org/all/20250909-gpio-mmio-gpio-conv-part4-v1-13-9f723dc3524a@linaro.org/ Suggested-by: Andy Shevchenko <andriy.shevchenko@intel.com> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Acked-by: Sudeep Holla <sudeep.holla@arm.com> Link: https://lore.kernel.org/r/20250910-make-compound-literals-normal-again-v1-1-076ee7738a0b@linaro.org Signed-off-by: Lee Jones <lee@kernel.org> 2025-10-01mfd: rz-mtu3: Fix MTU5 NFCR register offsetCosmin Tanislav1-1/+1 The NFCR register for MTU5 is at 0x1a95 offset according to Datasheet Page 725, Table 16.4. The address of all registers is offset by 0x1200, making the proper address of MTU5 NFCR register be 0x895. Cc: stable@vger.kernel.org Fixes: 654c293e1687 ("mfd: Add Renesas RZ/G2L MTU3a core driver") Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20250910175914.12956-1-cosmin-gabriel.tanislav.xa@renesas.com Signed-off-by: Lee Jones <lee@kernel.org> 2025-10-01mfd: max77705: Setup the core driver as an interrupt controllerDzmitry Sankouski1-21/+14 Current implementation describes only MFD's own topsys interrupts. However, max77705 has a register which indicates interrupt source, i.e. it acts as an interrupt controller. There's 4 interrupt sources in max77705: topsys, charger, fuelgauge, usb type-c manager. Setup max77705 MFD parent as an interrupt controller. Delete topsys interrupts because currently unused. Remove shared interrupt flag, because we're are an interrupt controller now, and subdevices should request interrupts from us. Fixes: c8d50f029748 ("mfd: Add new driver for MAX77705 PMIC") Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com> Link: https://lore.kernel.org/r/20250909-max77705-fix_interrupt_handling-v3-1-233c5a1a20b5@gmail.com Signed-off-by: Lee Jones <lee@kernel.org> 2025-10-01mfd: cs42l43: Remove IRQ masking in suspendCharles Keepax1-26/+0 Now the individual child drivers mask their own IRQs there is no need for the MFD code to do so anymore. Signed-off-by: Charles Keepax <ckeepax@opensource.cirrus.com> Link: https://lore.kernel.org/r/20250903094549.271068-7-ckeepax@opensource.cirrus.com Signed-off-by: Lee Jones <lee@kernel.org> 2025-10-01mfd: cs42l43: Move IRQ enable/disable to encompass force suspendCharles Keepax1-4/+4 As pm_runtime_force_suspend() will force the device state to suspend, the driver needs to ensure no IRQ handlers are currently running. If not those handlers may find they are now running on suspended hardware despite holding a PM runtime reference. disable_irq() will sync any currently running handlers, so move the IRQ disabling to cover the whole of the forced suspend state to avoid such race conditions. Signed-off-by: Charles Keepax <ckeepax@opensource.cirrus.com> Link: https://lore.kernel.org/r/20250903094549.271068-6-ckeepax@opensource.cirrus.com Signed-off-by: Lee Jones <lee@kernel.org> 2025-10-01mfd: ls2kbmc: Add Loongson-2K BMC reset function supportBinbin Zhou1-0/+339 Since the display is a sub-function of the Loongson-2K BMC, when the BMC reset, the entire BMC PCIe is disconnected, including the display which is interrupted. Quick overview of the entire LS2K BMC reset process: There are two types of reset methods: soft reset (BMC-initiated reboot of IPMI reset command) and BMC watchdog reset (watchdog timeout). First, regardless of the method, an interrupt is generated (PCIe interrupt for soft reset/GPIO interrupt for watchdog reset); Second, during the interrupt process, the system enters bmc_reset_work, clears the bus/IO/mem resources of the LS7A PCI-E bridge, waits for the BMC reset to begin, then restores the parent device's PCI configuration space, waits for the BMC reset to complete, and finally restores the BMC PCI configuration space. Display restoration occurs last. Co-developed-by: Chong Qiao <qiaochong@loongson.cn> Signed-off-by: Chong Qiao <qiaochong@loongson.cn> Reviewed-by: Huacai Chen <chenhuacai@loongson.cn> Acked-by: Corey Minyard <corey@minyard.net> Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn> Link: https://lore.kernel.org/r/de4e04b42ff9ee282f86f9bb9efbf959a9848205.1756987761.git.zhoubinbin@loongson.cn Signed-off-by: Lee Jones <lee@kernel.org> 2025-10-01mfd: ls2kbmc: Introduce Loongson-2K BMC core driverBinbin Zhou4-0/+210 The Loongson-2K Board Management Controller provides an PCIe interface to the host to access the feature implemented in the BMC. The BMC is assembled on a server similar to the server machine with Loongson-3 CPU. It supports multiple sub-devices like DRM and IPMI. Co-developed-by: Chong Qiao <qiaochong@loongson.cn> Signed-off-by: Chong Qiao <qiaochong@loongson.cn> Reviewed-by: Huacai Chen <chenhuacai@loongson.cn> Acked-by: Corey Minyard <corey@minyard.net> Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn> Link: https://lore.kernel.org/r/0dc1fd53020ce2562453961ffed2cd9eb8f359e1.1756987761.git.zhoubinbin@loongson.cn Signed-off-by: Lee Jones <lee@kernel.org> 2025-10-01mfd: bd71828, bd71815: Prepare for power-supply supportMatti Vaittinen2-9/+98 Add core support for ROHM BD718(15/28/78) PMIC's charger blocks. Signed-off-by: Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com> Signed-off-by: Andreas Kemnade <andreas@kemnade.info> Link: https://lore.kernel.org/r/20250821-bd71828-charger-v3-1-cc74ac4e0fb9@kemnade.info Signed-off-by: Lee Jones <lee@kernel.org> 2025-10-01dt-bindings: mfd: aspeed: Add AST2700 SCU compatiblesRyan Chen1-0/+4 Add SCU interrupt controller compatible strings for the AST2700 SoC: scu-ic0 to 3. This extends the MFD binding to support AST2700-based platforms. Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com> Acked-by: "Rob Herring (Arm)" <robh@kernel.org> Link: https://lore.kernel.org/r/20250831021438.976893-3-ryan_chen@aspeedtech.com Signed-off-by: Lee Jones <lee@kernel.org> 2025-10-01dt-bindings: mfd: Convert aspeed,ast2400-p2a-ctrl to DT schemaRob Herring (Arm)2-47/+32 Convert the aspeed,ast2x00-p2a-ctrl binding to DT schema format. The schema is simple enough to just add it to the parent aspeed,ast2x00-scu binding. Signed-off-by: "Rob Herring (Arm)" <robh@kernel.org> Acked-by: Andrew Jeffery <andrew@codeconstruct.com.au> Link: https://lore.kernel.org/r/20250829230450.1496151-1-robh@kernel.org Signed-off-by: Lee Jones <lee@kernel.org> 2025-10-01dt-bindings: mfd: fsl,mc13xxx: Add buttons nodeAlexander Kurz1-0/+70 Add a buttons node and properties describing the "ONOFD" (MC13783) and "PWRON" (MC13892/MC34708) buttons available in the fsl,mc13xxx PMIC ICs. Signed-off-by: Alexander Kurz <akurz@blala.de> Reviewed-by: "Rob Herring (Arm)" <robh@kernel.org> Link: https://lore.kernel.org/r/20250829201517.15374-7-akurz@blala.de Signed-off-by: Lee Jones <lee@kernel.org> 2025-10-01dt-bindings: mfd: fsl,mc13xxx: Convert txt to DT schemaAlexander Kurz2-156/+218 Convert the txt mc13xxx bindings to DT schema attempting to keep most information. The nodes codec and touchscreen are not part of the new schema since it was only briefly mentioned before. Following the convention, rename led-control to fsl,led-control. Signed-off-by: Alexander Kurz <akurz@blala.de> Reviewed-by: "Rob Herring (Arm)" <robh@kernel.org> Link: https://lore.kernel.org/r/20250829201517.15374-6-akurz@blala.de Signed-off-by: Lee Jones <lee@kernel.org> 2025-10-01mfd: macsmc: Add "apple,t8103-smc" compatibleJanne Grunau1-0/+1 After discussion with the devicetree maintainers we agreed to not extend lists with the generic compatible "apple,smc" anymore [1]. Use "apple,t8103-smc" as base compatible as it is the SoC the driver and bindings were written for. [1]: https://lore.kernel.org/asahi/12ab93b7-1fc2-4ce0-926e-c8141cfe81bf@kernel.org/ Signed-off-by: Janne Grunau <j@jannau.net> Link: https://lore.kernel.org/r/20250828-dt-apple-t6020-v1-18-507ba4c4b98e@jannau.net Signed-off-by: Lee Jones <lee@kernel.org> 2025-10-01mfd: core: Increment of_node's refcount before linking it to the platform deviceBastien Curutchet1-0/+1 When an MFD device is added, a platform_device is allocated. If this device is linked to a DT description, the corresponding OF node is linked to the new platform device but the OF node's refcount isn't incremented. As of_node_put() is called during the platform device release, it leads to a refcount underflow. Call of_node_get() to increment the OF node's refcount when the node is linked to the newly created platform device. Signed-off-by: Bastien Curutchet <bastien.curutchet@bootlin.com> Link: https://lore.kernel.org/r/20250820-mfd-refcount-v1-1-6dcb5eb41756@bootlin.com Signed-off-by: Lee Jones <lee@kernel.org> 2025-10-01dt-bindings: mfd: syscon: Document the control-scb syscon on PolarFire SoCConor Dooley1-0/+2 The "control-scb" region, contains the "tvs" temperature and voltage sensors and the control/status registers for the system controller's mailbox. The mailbox has a dedicated node, so there's no need for a child node describing it, looking the syscon up by compatible is sufficient. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20250901-shorten-yahoo-223aeaecd290@spud Signed-off-by: Lee Jones <lee@kernel.org> 2025-10-01mfd: simple-mfd-i2c: Add SpacemiT P1 supportAlex Elder2-0/+30 Enable support for the RTC and regulators found in the SpacemiT P1 PMIC. Support is implemented by the simple I2C MFD driver. The P1 PMIC is normally implemented with the SpacemiT K1 SoC. This PMIC provides 6 buck converters and 12 LDO regulators. It also implements a switch, watchdog timer, real-time clock, and more. Initially its RTC and regulators are supported. Signed-off-by: Alex Elder <elder@riscstar.com> Link: https://lore.kernel.org/r/20250825172057.163883-3-elder@riscstar.com Signed-off-by: Lee Jones <lee@kernel.org>