aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/i915/display/intel_cx0_phy.c (follow)
AgeCommit message (Expand)AuthorFilesLines
2024-10-30drm/i915/display: use x100 version for full version and releaseJani Nikula1-2/+2
2024-10-30drm/i915/cx0: convert to struct intel_displayJani Nikula1-156/+181
2024-10-29drm/i915/cx0: Remove bus reset after every c10 transactionClint Taylor1-2/+4
2024-10-29drm/i915/cx0: Extend C10 check to PTLDnyaneshwar Bhadane1-0/+3
2024-10-29drm/i915/xe3lpd: Add check to see if edp over type c is allowedSuraj Kandpal1-0/+3
2024-10-29drm/i915/display: convert I915_STATE_WARN() to struct intel_displayJani Nikula1-38/+38
2024-10-28drm/i915/xe2lpd: Update C20 algorithm to include tx_miscGustavo Sousa1-1/+8
2024-10-28drm/i915/cx0: Pass crtc_state to intel_c20_compute_hdmi_tmds_pll()Gustavo Sousa1-6/+6
2024-10-23drm/i915/xe3lpd: Add condition for EDP to powerdown P2.PGSuraj Kandpal1-1/+2
2024-10-23drm/i915/xe3lpd: Add C20 Phy consolidated programming tableSuraj Kandpal1-3/+23
2024-10-23drm/i915/panel: Convert panel code to intel_displayVille Syrjälä1-1/+2
2024-10-09drm/i915/mtl: Update PLL c20 phy value for DP uhbr20Dnyaneshwar Bhadane1-4/+4
2024-06-28drm/i915/mtl: Skip PLL state verification in TBT modeImre Deak1-3/+8
2024-05-30drm/i915/display: Add compare config for MTL+ platformsMika Kahola1-6/+71
2024-05-30drm/i915/display: Revert "drm/i915/display: Skip C10 state verification in ca...Mika Kahola1-3/+0
2024-05-03drm/i915/xe2hpd: update pll values in sync with BspecRavi Kumar Vodapalli1-2/+44
2024-05-03drm/i915/xe2hpd: Add support for eDP PLL configurationBalasubramani Vivekanandan1-1/+146
2024-05-03drm/i915/xe2hpd: Add new C20 PHY SRAM addressBalasubramani Vivekanandan1-24/+41
2024-05-03drm/i915/xe2hpd: Properly disable power in port AJosé Roberto de Souza1-3/+14
2024-05-03drm/i915/bmg: Lane reversal requires writes to both context lanesClint Taylor1-5/+5
2024-05-03drm/i915/display: Calculate crtc clock rate based on PLL parametersMika Kahola1-1/+2
2024-04-17drm/i915: Suck snps/cx0 PLL states into dpll_hw_stateVille Syrjälä1-10/+10
2024-03-26drm/i915/de: register wait function renamesJani Nikula1-34/+34
2024-03-21drm/i915/cx0: pass encoder instead of i915 and port aroundJani Nikula1-122/+136
2024-03-21drm/i915/cx0: remove the unused intel_is_c10phy()Jani Nikula1-10/+4
2024-03-21drm/i915/display: use intel_encoder_is/to_* functionsJani Nikula1-25/+11
2024-03-21drm/i915/display: add intel_encoder_is_*() and _to_*() functionsJani Nikula1-0/+9
2024-02-14drm/i915/display: update pll values in sync with Bspec for MTLRavi Kumar Vodapalli1-16/+16
2024-01-30drm/i915/xe2lpd: Move registers to PICALucas De Marchi1-42/+45
2024-01-08drm/i915/display: Use helper to select C20 MPLLA/BMika Kahola1-6/+11
2024-01-04drm/i915/display: Skip C10 state verification in case of fastsetMika Kahola1-0/+3
2024-01-04drm/i915/display: Cleanup mplla/mpllb selectionMika Kahola1-24/+15
2024-01-04drm/i915/display: Store hw clock for C20Mika Kahola1-45/+52
2024-01-04drm/i915/display: Fix C20 pll selection for state verificationMika Kahola1-10/+15
2023-12-15drm/i915/mtl: Fix HDMI/DP PLL clock selectionImre Deak1-1/+2
2023-12-08drm/i915/mtl: Rename the link_bit_rate to clock in C20 pll_stateRadhakrishna Sripada1-21/+21
2023-12-08drm/i915/mtl: Remove misleading "clock" field from C20 pll_stateRadhakrishna Sripada1-18/+0
2023-12-08drm/i915/mtl: Use port clock compatible numbers for C20 phyRadhakrishna Sripada1-21/+22
2023-12-01drm/i915/display: Skip state verification with TBT-ALT modeMika Kahola1-1/+10
2023-11-13drm/i915/mtl: C20 state verificationMika Kahola1-34/+86
2023-10-29drm/i915/display: Abstract C10/C20 pll calculationLucas De Marchi1-4/+16
2023-10-29drm/i915/display: Abstract C10/C20 pll hw readoutLucas De Marchi1-4/+16
2023-10-29drm/i915/lnl: Extend C10/C20 phyLucas De Marchi1-1/+1
2023-10-26drm/i915/display: Reset message bus after each read/write operationMika Kahola1-0/+14
2023-10-16drm/i915/display: Clean up zero initializersVille Syrjälä1-1/+1
2023-10-11drm/i915/cx0: Only clear/set the Pipe Reset bit of the PHY Lanes OwnedKhaled Almahallawy1-2/+1
2023-10-07drm/i915: Simplify snps/c10x DPLL state checker calling convetionVille Syrjälä1-2/+3
2023-10-07drm/i915: Constify the snps/c10x PLL state checkersVille Syrjälä1-2/+2
2023-09-18drm/i915/cx0: Add step for programming msgbus timerGustavo Sousa1-47/+40
2023-09-06drm/i915/cx0: Check and increase msgbus timeout thresholdGustavo Sousa1-0/+39
generated by cgit v1.2.3 (git 2.39.1) at 2026-01-03 01:10:50 +0000